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Index: sys/dev/rt/if_rt.c
===================================================================
--- sys/dev/rt/if_rt.c
+++ sys/dev/rt/if_rt.c
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2015, Stanislav Galabov
+ * Copyright (c) 2015-2016, Stanislav Galabov
* Copyright (c) 2014, Aleksandr A. Mityaev
* Copyright (c) 2011, Aleksandr Rybalko
* based on hard work
@@ -54,6 +54,7 @@
#include <vm/vm_param.h>
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/pmap.h>
#include <sys/bus.h>
#include <sys/rman.h>
@@ -69,8 +70,10 @@
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
+#if 0
#include <mips/rt305x/rt305x_sysctlvar.h>
#include <mips/rt305x/rt305xreg.h>
+#endif
#ifdef IF_RT_PHY_SUPPORT
#include "miibus_if.h"
@@ -89,19 +92,20 @@
#define RT_TX_WATCHDOG_TIMEOUT 5
#define RT_CHIPID_RT3050 0x3050
-#define RT_CHIPID_RT3052 0x3052
#define RT_CHIPID_RT5350 0x5350
-#define RT_CHIPID_RT6855 0x6855
#define RT_CHIPID_MT7620 0x7620
+#define RT_CHIPID_MT7621 0x7621
#ifdef FDT
/* more specific and new models should go first */
static const struct ofw_compat_data rt_compat_data[] = {
- { "ralink,rt6855-eth", (uintptr_t)RT_CHIPID_RT6855 },
- { "ralink,rt5350-eth", (uintptr_t)RT_CHIPID_RT5350 },
- { "ralink,rt3052-eth", (uintptr_t)RT_CHIPID_RT3052 },
- { "ralink,rt305x-eth", (uintptr_t)RT_CHIPID_RT3050 },
- { NULL, (uintptr_t)NULL }
+ { "ralink,rt3050-eth", RT_CHIPID_RT3050 },
+ { "ralink,rt3352-eth", RT_CHIPID_RT3050 },
+ { "ralink,rt3883-eth", RT_CHIPID_RT3050 },
+ { "ralink,rt5350-eth", RT_CHIPID_RT5350 },
+ { "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
+ { "ralink,mt7621-eth", RT_CHIPID_MT7621 },
+ { NULL, 0 }
};
#endif
@@ -182,21 +186,23 @@
const struct ofw_compat_data * cd;
cd = ofw_bus_search_compatible(dev, rt_compat_data);
- if (cd->ocd_data == (uintptr_t)NULL)
+ if (cd->ocd_data == 0)
return (ENXIO);
sc->rt_chipid = (unsigned int)(cd->ocd_data);
#else
#if defined(MT7620)
sc->rt_chipid = RT_CHIPID_MT7620;
+#elif defined(MT7621)
+ sc->rt_chipid = RT_CHIPID_MT7621;
#elif defined(RT5350)
sc->rt_chipid = RT_CHIPID_RT5350;
#else
sc->rt_chipid = RT_CHIPID_RT3050;
#endif
#endif
- snprintf(buf, sizeof(buf), "Ralink RT%x onChip Ethernet driver",
- sc->rt_chipid);
+ snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver",
+ sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid);
device_set_desc_copy(dev, buf);
return (BUS_PROBE_GENERIC);
}
@@ -373,12 +379,26 @@
/* Reset hardware */
reset_freng(sc);
+
+
+ if (sc->rt_chipid == RT_CHIPID_MT7620) {
+ sc->csum_fail_ip = (1<<25);
+ sc->csum_fail_l4 = (1<<22);
+ } else if (sc->rt_chipid == RT_CHIPID_MT7621) {
+ sc->csum_fail_ip = (1<<26);
+ sc->csum_fail_l4 = (1<<23);
+ } else {
+ sc->csum_fail_ip = (1<<29);//RXDSXR_SRC_IP_CSUM_FAIL;
+ sc->csum_fail_l4 = (1<<28);//RXDSXR_SRC_L4_CSUM_FAIL;
+ }
/* Fill in soc-specific registers map */
switch(sc->rt_chipid) {
case RT_CHIPID_MT7620:
+ case RT_CHIPID_MT7621:
case RT_CHIPID_RT5350:
- device_printf(dev, "RT%x Ethernet MAC (rev 0x%08x)\n",
+ device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n",
+ sc->rt_chipid >= 0x7600 ? 'M' : 'R',
sc->rt_chipid, sc->mac_rev);
/* RT5350: No GDMA, PSE, CDMA, PPE */
RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1
@@ -406,10 +426,6 @@
sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE;
sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE;
break;
- case RT_CHIPID_RT6855:
- device_printf(dev, "RT6855 Ethernet MAC (rev 0x%08x)\n",
- sc->mac_rev);
- break;
default:
device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
sc->mac_rev);
@@ -533,7 +549,8 @@
/* set up interrupt */
error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
NULL, (sc->rt_chipid == RT_CHIPID_RT5350 ||
- sc->rt_chipid == RT_CHIPID_MT7620) ? rt_rt5350_intr : rt_intr,
+ sc->rt_chipid == RT_CHIPID_MT7620 ||
+ sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr,
sc, &sc->irqh);
if (error != 0) {
printf("%s: could not set up interrupt\n",
@@ -763,7 +780,7 @@
//rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
/* Fwd to CPU (uni|broad|multi)cast and Unknown */
- if(sc->rt_chipid == RT_CHIPID_RT3050 || sc->rt_chipid == RT_CHIPID_RT3052)
+ if(sc->rt_chipid == RT_CHIPID_RT3050)
RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
(
GDM_ICS_EN | /* Enable IP Csum */
@@ -831,7 +848,8 @@
/* write back DDONE, 16byte burst enable RX/TX DMA */
tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN;
- if (sc->rt_chipid == RT_CHIPID_MT7620)
+ if (sc->rt_chipid == RT_CHIPID_MT7620 ||
+ sc->rt_chipid == RT_CHIPID_MT7621)
tmp |= (1<<31);
RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
@@ -843,7 +861,8 @@
/* enable interrupts */
if (sc->rt_chipid == RT_CHIPID_RT5350 ||
- sc->rt_chipid == RT_CHIPID_MT7620)
+ sc->rt_chipid == RT_CHIPID_MT7620 ||
+ sc->rt_chipid == RT_CHIPID_MT7621)
tmp = RT5350_INT_TX_COHERENT |
RT5350_INT_RX_COHERENT |
RT5350_INT_TXQ3_DONE |
@@ -945,7 +964,8 @@
RT_WRITE(sc, sc->fe_int_enable, 0);
if(sc->rt_chipid == RT_CHIPID_RT5350 ||
- sc->rt_chipid == RT_CHIPID_MT7620) {
+ sc->rt_chipid == RT_CHIPID_MT7620 ||
+ sc->rt_chipid == RT_CHIPID_MT7621) {
} else {
/* reset adapter */
RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
@@ -1055,22 +1075,29 @@
/* TODO: this needs to be refined as MT7620 for example has
* a different word3 layout than RT305x and RT5350 (the last
- * one doesn't use word3 at all).
+ * one doesn't use word3 at all). And so does MT7621...
*/
- /* Set destination */
- if (sc->rt_chipid != RT_CHIPID_MT7620)
- desc->dst = (TXDSCR_DST_PORT_GDMA1);
-
- if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
- desc->dst |= (TXDSCR_IP_CSUM_GEN|TXDSCR_UDP_CSUM_GEN|
- TXDSCR_TCP_CSUM_GEN);
- /* Set queue id */
- desc->qn = qid;
- /* No PPPoE */
- desc->pppoe = 0;
- /* No VLAN */
- desc->vid = 0;
+ if (sc->rt_chipid != RT_CHIPID_MT7621) {
+ /* Set destination */
+ if (sc->rt_chipid != RT_CHIPID_MT7620)
+ desc->dst = (TXDSCR_DST_PORT_GDMA1);
+
+ if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
+ desc->dst |= (TXDSCR_IP_CSUM_GEN |
+ TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN);
+ /* Set queue id */
+ desc->qn = qid;
+ /* No PPPoE */
+ desc->pppoe = 0;
+ /* No VLAN */
+ desc->vid = 0;
+ } else {
+ desc->vid = 0;
+ desc->pppoe = 0;
+ desc->qn = 0;
+ desc->dst = 2;
+ }
desc->sdp0 = htole32(dma_seg[i].ds_addr);
desc->sdl0 = htole16(dma_seg[i].ds_len |
@@ -1714,7 +1741,8 @@
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
if(sc->rt_chipid == RT_CHIPID_RT5350 ||
- sc->rt_chipid == RT_CHIPID_MT7620)
+ sc->rt_chipid == RT_CHIPID_MT7620 ||
+ sc->rt_chipid == RT_CHIPID_MT7621)
intr_mask = (
RT5350_INT_TXQ3_DONE |
RT5350_INT_TXQ2_DONE |
@@ -1870,15 +1898,13 @@
BUS_DMASYNC_PREREAD);
m = data->m;
- desc_flags = desc->src;
+ desc_flags = desc->word3;
data->m = mnew;
/* Add 2 for proper align of RX IP header */
desc->sdp0 = htole32(segs[0].ds_addr+2);
desc->sdl0 = htole32(segs[0].ds_len-2);
- desc->src = 0;
- desc->ai = 0;
- desc->foe = 0;
+ desc->word3 = 0;
RT_DPRINTF(sc, RT_DEBUG_RX,
"Rx frame: rxdesc flags=0x%08x\n", desc_flags);
@@ -1891,8 +1917,7 @@
/* check for crc errors */
if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
/*check for valid checksum*/
- if (desc_flags & (RXDSXR_SRC_IP_CSUM_FAIL|
- RXDSXR_SRC_L4_CSUM_FAIL)) {
+ if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) {
RT_DPRINTF(sc, RT_DEBUG_RX,
"rxdesc: crc error\n");
@@ -1903,7 +1928,7 @@
goto skip;
}
}
- if ((desc_flags & RXDSXR_SRC_IP_CSUM_FAIL) != 0) {
+ if ((desc_flags & sc->csum_fail_ip) == 0) {
m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
m->m_pkthdr.csum_data = 0xffff;
@@ -2031,7 +2056,8 @@
int ntries;
#endif
if(sc->rt_chipid != RT_CHIPID_RT5350 &&
- sc->rt_chipid != RT_CHIPID_MT7620) {
+ sc->rt_chipid != RT_CHIPID_MT7620 &&
+ sc->rt_chipid != RT_CHIPID_MT7621) {
tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
RT_DPRINTF(sc, RT_DEBUG_WATCHDOG,
Index: sys/dev/rt/if_rtvar.h
===================================================================
--- sys/dev/rt/if_rtvar.h
+++ sys/dev/rt/if_rtvar.h
@@ -121,6 +121,7 @@
uint16_t sdl1;
uint16_t sdl0;
uint32_t sdp1;
+#if 0
uint16_t foe;
#define RXDSXR_FOE_ENTRY_VALID 0x40
#define RXDSXR_FOE_ENTRY_MASK 0x3f
@@ -134,6 +135,8 @@
#define RXDSXR_SRC_L4_CSUM_FAIL 0x10
#define RXDSXR_SRC_AIS 0x08
#define RXDSXR_SRC_PORT_MASK 0x07
+#endif
+ uint32_t word3;
} __packed;
struct rt_softc_rx_data
@@ -263,6 +266,8 @@
uint32_t rt_chipid;
/* chip specific registers config */
int rx_ring_count;
+ uint32_t csum_fail_l4;
+ uint32_t csum_fail_ip;
uint32_t int_rx_done_mask;
uint32_t int_tx_done_mask;
uint32_t delay_int_cfg;

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