D17952.id50292.diff
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	Index: sys/riscv/include/cpufunc.h
	===================================================================
	--- sys/riscv/include/cpufunc.h
	+++ sys/riscv/include/cpufunc.h
	@@ -104,6 +104,11 @@
	__asm __volatile("sfence.vma %0" :: "r" (addr) : "memory");
	}

	+#define rdcycle() csr_read64(cycle)
	+#define rdtime() csr_read64(time)
	+#define rdinstret() csr_read64(instret)
	+#define rdhpmcounter(n) csr_read64(hpmcounter##n)
	+
	#define cpufunc_nullop() riscv_nullop()

	void riscv_nullop(void);
	Index: sys/riscv/include/riscvreg.h
	===================================================================
	--- sys/riscv/include/riscvreg.h
	+++ sys/riscv/include/riscvreg.h
	@@ -223,4 +223,23 @@
	val; \
	})

	+#if __riscv_xlen == 32
	+#define csr_read64(csr) \
	+({ uint64_t val; \
	+ uint32_t high, low; \
	+ __asm __volatile("1: " \
	+ "csrr t0, " #csr "h\n" \
	+ "csrr %0, " #csr "\n" \
	+ "csrr %1, " #csr "h\n" \
	+ "bne t0, %1, 1b" \
	+ : "=r" (low), "=r" (high) \
	+ : \
	+ : "t0"); \
	+ val = (low \| ((uint64_t)high << 32)); \
	+ val; \
	+})
	+#else
	+#define csr_read64(csr) (uint64_t)csr_read(csr)
	+#endif
	+
	#endif /* !_MACHINE_RISCVREG_H_ */