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diff --git a/sys/dev/mmc/mmcreg.h b/sys/dev/mmc/mmcreg.h
--- a/sys/dev/mmc/mmcreg.h
+++ b/sys/dev/mmc/mmcreg.h
@@ -137,6 +137,8 @@
#define R1_CARD_ECC_FAILED (1u << 21) /* erx, c */
#define R1_CC_ERROR (1u << 20) /* erx, c */
#define R1_ERROR (1u << 19) /* erx, c */
+#define R1_UNDERRUN (1u << 18) /* ex, c */
+#define R1_OVERRUN (1u << 17) /* ex, c */
#define R1_CSD_OVERWRITE (1u << 16) /* erx, c */
#define R1_WP_ERASE_SKIP (1u << 15) /* erx, c */
#define R1_CARD_ECC_DISABLED (1u << 14) /* sx, a */
@@ -144,6 +146,7 @@
#define R1_CURRENT_STATE_MASK (0xfu << 9) /* sx, b */
#define R1_READY_FOR_DATA (1u << 8) /* sx, a */
#define R1_SWITCH_ERROR (1u << 7) /* sx, c */
+#define R1_EXCEPTION_EVENT (1u << 6) /* sr, a */
#define R1_APP_CMD (1u << 5) /* sr, c */
#define R1_AKE_SEQ_ERROR (1u << 3) /* er, c */
#define R1_STATUS(x) ((x) & 0xFFFFE000)
@@ -158,6 +161,25 @@
#define R1_STATE_PRG 7
#define R1_STATE_DIS 8
+#define R1_SPI_IDLE (1u << 0)
+#define R1_SPI_ERASE_RESET (1u << 1)
+#define R1_SPI_ILLEGAL_COMMAND (1u << 2)
+#define R1_SPI_COM_CRC (1u << 3)
+#define R1_SPI_ERASE_SEQ (1u << 4)
+#define R1_SPI_ADDRESS (1u << 5)
+#define R1_SPI_PARAMETER (1u << 6)
+/* R1 bit 7: always zero */
+#define R2_SPI_CARD_LOCKED (1u << 8)
+#define R2_SPI_WP_ERASE_SKIP (1u << 9)
+#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
+#define R2_SPI_ERROR (1u << 10)
+#define R2_SPI_CC_ERROR (1u << 11)
+#define R2_SPI_CARD_ECC_ERROR (1u << 12)
+#define R2_SPI_WP_VIOLATION (1u << 13)
+#define R2_SPI_ERASE_PARAM (1u << 14)
+#define R2_SPI_OUT_OF_RANGE (1u << 15)
+#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
+
/* R4 responses (SDIO) */
#define R4_IO_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x3)
#define R4_IO_MEM_PRESENT (0x1 << 27)
@@ -196,7 +218,7 @@
#define MMC_DATA_READ (1UL << 1)
#define MMC_DATA_STREAM (1UL << 2)
#define MMC_DATA_MULTI (1UL << 3)
-#define MMC_DATA_BLOCK_SIZE (1UL << 4)
+#define MMC_DATA_BLOCK_SIZE (1UL << 4)
struct mmc_request *mrq;
size_t block_size; /* block size for CMD53 */
size_t block_count; /* block count for CMD53 */
@@ -235,18 +257,22 @@
#define MMC_SEND_CSD 9
#define MMC_SEND_CID 10
#define MMC_READ_DAT_UNTIL_STOP 11
+#define SD_SWITCH_VOLTAGE 11
#define MMC_STOP_TRANSMISSION 12
#define MMC_SEND_STATUS 13
#define MMC_BUSTEST_R 14
#define MMC_GO_INACTIVE_STATE 15
#define MMC_BUSTEST_W 19
+#define MMC_SPI_READ_OCR 58
+#define MMC_SPI_CRC_ON_OFF 59
/* Class 2: Block oriented read commands */
-#define MMC_SET_BLOCKLEN 16
-#define MMC_READ_SINGLE_BLOCK 17
-#define MMC_READ_MULTIPLE_BLOCK 18
-#define MMC_SEND_TUNING_BLOCK 19
-#define MMC_SEND_TUNING_BLOCK_HS200 21
+#define MMC_SET_BLOCKLEN 16
+#define MMC_READ_SINGLE_BLOCK 17
+#define MMC_READ_MULTIPLE_BLOCK 18
+#define MMC_SEND_TUNING_BLOCK 19
+#define MMC_SEND_TUNING_BLOCK_HS200 21
+#define SD_ADDR_EXT 22
/* Class 3: Stream write commands */
#define MMC_WRITE_DAT_UNTIL_STOP 20
@@ -347,6 +373,15 @@
/* reserved: 50 */
/* reserved: 57 */
+/* Class 11: Extension */
+#define MMC_QUE_TASK_PARAMS 44
+#define MMC_QUE_TASK_ADDR 45
+#define MMC_EXECUTE_READ_TASK 46
+#define MMC_EXECUTE_WRITE_TASK 47
+#define MMC_CMDQ_TASK_MGMT 48
+#define SD_READ_EXTR_SINGLE 48
+#define SD_WRITE_EXTR_SINGLE 49
+
/* Application specific commands for SD */
#define ACMD_SET_BUS_WIDTH 6
#define ACMD_SD_STATUS 13
@@ -358,46 +393,178 @@
/*
* EXT_CSD fields
+ * R : Read only.
+ * W : One time programmable and not readable.
+ * R/W : One time programmable and readable.
+ * W/E : Multiple writable with value kept after power failure,
+ * H/W reset assertion and any CMD0 reset and not readable.
+ * R/W/E : Multiple writable with value kept after power failure,
+ * H/W reset assertion and any CMD0 reset and readable.
+ * R/W/C_P : Writable after value cleared by power failure and
+ * HW/rest assertion (the value not cleared by CMD0
+ * reset) and readable.
+ * R/W/E_P : Multiple writable with value reset after power
+ * failure, H/W reset assertion and any CMD0 reset
+ * and readable.
+ * W/E_P : Multiple writable with value reset
*/
-#define EXT_CSD_FLUSH_CACHE 32 /* W/E */
-#define EXT_CSD_CACHE_CTRL 33 /* R/W/E */
-#define EXT_CSD_EXT_PART_ATTR 52 /* R/W, 2 bytes */
-#define EXT_CSD_ENH_START_ADDR 136 /* R/W, 4 bytes */
-#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W, 3 bytes */
-#define EXT_CSD_GP_SIZE_MULT 143 /* R/W, 12 bytes */
-#define EXT_CSD_PART_SET 155 /* R/W */
-#define EXT_CSD_PART_ATTR 156 /* R/W */
-#define EXT_CSD_PART_SUPPORT 160 /* RO */
-#define EXT_CSD_RPMB_MULT 168 /* RO */
-#define EXT_CSD_BOOT_WP_STATUS 174 /* RO */
-#define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */
-#define EXT_CSD_PART_CONFIG 179 /* R/W */
-#define EXT_CSD_BUS_WIDTH 183 /* R/W */
-#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
-#define EXT_CSD_HS_TIMING 185 /* R/W */
-#define EXT_CSD_POWER_CLASS 187 /* R/W */
-#define EXT_CSD_CARD_TYPE 196 /* RO */
-#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
-#define EXT_CSD_REV 192 /* RO */
-#define EXT_CSD_PART_SWITCH_TO 199 /* RO */
-#define EXT_CSD_PWR_CL_52_195 200 /* RO */
-#define EXT_CSD_PWR_CL_26_195 201 /* RO */
-#define EXT_CSD_PWR_CL_52_360 202 /* RO */
-#define EXT_CSD_PWR_CL_26_360 203 /* RO */
-#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
-#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
-#define EXT_CSD_ERASE_TO_MULT 223 /* RO */
-#define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */
-#define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */
-#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
-#define EXT_CSD_PWR_CL_200_195 236 /* RO */
-#define EXT_CSD_PWR_CL_200_360 237 /* RO */
-#define EXT_CSD_PWR_CL_52_195_DDR 238 /* RO */
-#define EXT_CSD_PWR_CL_52_360_DDR 239 /* RO */
-#define EXT_CSD_CACHE_FLUSH_POLICY 249 /* RO */
-#define EXT_CSD_GEN_CMD6_TIME 248 /* RO */
-#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
-#define EXT_CSD_PWR_CL_200_360_DDR 253 /* RO */
+#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W/E_P */
+#define EXT_CSD_SECURE_REMOVAL_TYPE 16 /* R/W & R */
+#define EXT_CSD_PRODUCT_STATE_AWARENESS_ENABLEMENT 17 /* R/W/E & R */
+#define EXT_CSD_MAX_PRE_LOADING_DATA_SIZE 18 /* R, 4 bytes */
+#define EXT_CSD_PRE_LOADING_DATA_SIZE 22 /* R/W/E_P, 4 bytes */
+#define EXT_CSD_FFU_STATUS 26 /* R */
+ /* bytes 27-28 are reserved */
+#define EXT_CSD_MODE_OPERATION_CODES 29 /* W/E_P */
+#define EXT_CSD_MODE_CONFIG 30 /* R/W/E_P */
+#define EXT_CSD_BARRIER_CTRL 31 /* R/W */
+#define EXT_CSD_FLUSH_CACHE 32 /* W/E_P */
+#define EXT_CSD_CACHE_CTRL 33 /* R/W/E_P */
+#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W/E_P */
+#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* R */
+#define EXT_CSD_PACKED_COMMAND_STATUS 36 /* R */
+#define EXT_CSD_CONTEXT_CONF 37 /* R/W/E_P, 15 bytes */
+#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE 52 /* R/W, 2 bytes */
+#define EXT_CSD_EXCEPTION_EVENTS_STATUS 54 /* R, 2 bytes */
+#define EXT_CSD_EXCEPTION_EVENTS_CTRL 56 /* R/W/E_P, 2 bytes */
+#define EXT_CSD_DYNCAP_NEEDED 58 /* R */
+#define EXT_CSD_CLASS_6_CTRL 59 /* R/W/E_P */
+#define EXT_CSD_INI_TIMEOUT_EMU 60 /* R */
+#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
+#define EXT_CSD_USE_NATIVE_SECTOR 62 /* R/W */
+#define EXT_CSD_NATIVE_SECTOR_SIZE 63 /* R */
+#define EXT_CSD_VENDOR_SPECIFIC_FIELD 64 /* <vendor specific>, 64 bytes */
+ /* bytes 128-129 are reserved */
+#define EXT_CSD_PROGRAM_CID_CSD_DDR_SUPPORT 130 /* R */
+#define EXT_CSD_PERIODIC_WAKEUP 131 /* R/W/E */
+#define EXT_CSD_TCASE_SUPPORT 132 /* W/E_P */
+#define EXT_CSD_PRODUCTION_STATE_AWARENESS 133 /* R/W/E */
+#define EXT_CSD_SEC_BAD_BLK_MGMNT 134 /* R/W */
+ /* byte 135 is reserved */
+#define EXT_CSD_ENH_START_ADDR 136 /* R/W, 4 bytes */
+#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W, 3 bytes */
+#define EXT_CSD_GP_SIZE_MULT 143 /* R/W, 12 bytes */
+#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
+#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
+#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R, 3 bytes */
+#define EXT_CSD_PARTITIONING_SUPPORT 160 /* R */
+#define EXT_CSD_HPI_MGMT 161 /* R/W/E_P */
+#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
+#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
+#define EXT_CSD_BKOPS_START 164 /* W/E_P */
+#define EXT_CSD_SANITIZE_START 165 /* W/E_P */
+#define EXT_CSD_WR_REL_PARAM 166 /* R */
+#define EXT_CSD_WR_REL_SET 167 /* R/W */
+#define EXT_CSD_RPMB_SIZE_MULT 168 /* R */
+#define EXT_CSD_FW_CONFIG 169 /* R/W */
+ /* byte 170 is reserved */
+#define EXT_CSD_USER_WP 171 /* R/W, R/W/C_P & R/W/E_P */
+ /* byte 172 is reserved */
+#define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */
+#define EXT_CSD_BOOT_WP_STATUS 174 /* R */
+#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W/E_P */
+ /* byte 176 is reserved */
+#define EXT_CSD_BOOT_BUS_CONDITIONS 177 /* R/W/E */
+#define EXT_CSD_BOOT_CONFIG_PROT 178 /* R/W & R/W/C_P */
+#define EXT_CSD_PARTITION_CONFIG 179 /* R/W/E & R/W/E_P */
+ /* byte 180 is reserved */
+#define EXT_CSD_ERASED_MEM_CONT 181 /* R */
+ /* byte 182 is reserved */
+#define EXT_CSD_BUS_WIDTH 183 /* W/E_P */
+#define EXT_CSD_STROBE_SUPPORT 184 /* R */
+#define EXT_CSD_HS_TIMING 185 /* R/W/E_P */
+ /* byte 186 is reserved */
+#define EXT_CSD_POWER_CLASS 187 /* R/W/E_P */
+ /* byte 188 is reserved */
+#define EXT_CSD_CMD_SET_REV 189 /* R */
+ /* byte 190 is reserved */
+#define EXT_CSD_CMD_SET 191 /* R/W/E_P */
+#define EXT_CSD_REV 192 /* R */
+ /* byte 193 is reserved */
+#define EXT_CSD_CSD_STRUCTURE 194 /* R */
+ /* byte 195 is reserved */
+#define EXT_CSD_DEVICE_TYPE 196 /* R */
+#define EXT_CSD_DRIVER_STRENGTH 197 /* R */
+#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* R */
+#define EXT_CSD_PARTITION_SWITCH_TIME 199 /* R */
+#define EXT_CSD_PWR_CL_52_195 200 /* R */
+#define EXT_CSD_PWR_CL_26_195 201 /* R */
+#define EXT_CSD_PWR_CL_52_360 202 /* R */
+#define EXT_CSD_PWR_CL_26_360 203 /* R */
+ /* byte 204 is reserved */
+#define EXT_CSD_MIN_PERF_R_4_26 205 /* R */
+#define EXT_CSD_MIN_PERF_W_4_26 206 /* R */
+#define EXT_CSD_MIN_PERF_R_8_26_4_52 207 /* R */
+#define EXT_CSD_MIN_PERF_W_8_26_4_52 208 /* R */
+#define EXT_CSD_MIN_PERF_R_8_52 209 /* R */
+#define EXT_CSD_MIN_PERF_W_8_52 210 /* R */
+#define EXT_CSD_SECURE_WP_INFO 211 /* R */
+#define EXT_CSD_SEC_COUNT 212 /* R, 4 bytes */
+#define EXT_CSD_SLEEP_NOTIFICATION_TIME 216 /* R */
+#define EXT_CSD_S_A_TIMEOUT 217 /* R */
+#define EXT_CSD_PRODUCTION_STATE_AWARENESS_TIMEOUT 218 /* R */
+#define EXT_CSD_S_C_VCCQ 219 /* R */
+#define EXT_CSD_S_C_VCC 220 /* R */
+#define EXT_CSD_HC_WP_GRP_SIZE 221 /* R */
+#define EXT_CSD_REL_WR_SEC_C 222 /* R */
+#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* R */
+#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* R */
+#define EXT_CSD_ACC_SIZE 225 /* R */
+#define EXT_CSD_BOOT_SIZE_MULT 226 /* R */
+ /* byte 227 is reserved */
+#define EXT_CSD_BOOT_INFO 228 /* R */
+#define EXT_CSD_SEC_TRIM_MULT 229 /* R */
+#define EXT_CSD_SEC_ERASE_MULT 230 /* R */
+#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* R */
+#define EXT_CSD_TRIM_MULT 232 /* R */
+ /* byte 233 is reserved */
+#define EXT_CSD_MIN_PERF_DDR_R_8_52 234 /* R */
+#define EXT_CSD_MIN_PERF_DDR_W_8_52 235 /* R */
+#define EXT_CSD_PWR_CL_200_130 236 /* R */
+#define EXT_CSD_PWR_CL_200_195 237 /* R */
+#define EXT_CSD_PWR_CL_DDR_52_195 238 /* R */
+#define EXT_CSD_PWR_CL_DDR_52_360 239 /* R */
+#define EXT_CSD_CACHE_FLUSH_POLICY 240 /* R */
+#define EXT_CSD_INI_TIMEOUT_AP 241 /* R */
+#define EXT_CSD_CORRECTLY_PRG_SECTORS_NUM 242 /* R, 4 bytes */
+#define EXT_CSD_BKOPS_STATUS 246 /* R */
+#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* R */
+#define EXT_CSD_GENERIC_CMD6_TIME 248 /* R */
+#define EXT_CSD_CACHE_SIZE 249 /* R, 4 bytes */
+#define EXT_CSD_PWR_CL_DDR_200_360 253 /* R */
+#define EXT_CSD_PWR_CL_DDR_200_360 253 /* R */
+#define EXT_CSD_FIRMWARE_VERSION 254 /* R, 8 bytes */
+#define EXT_CSD_DEVICE_VERSION 262 /* R, 2 bytes */
+#define EXT_CSD_OPTIMAL_TRIM_UNIT_SIZE 264 /* R */
+#define EXT_CSD_OPTIMAL_WRITE_SIZE 265 /* R */
+#define EXT_CSD_OPTIMAL_READ_SIZE 266 /* R */
+#define EXT_CSD_PRE_EOL_INFO 267 /* R */
+#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* R */
+#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* R */
+#define EXT_CSD_VENDOR_PROPRIETARY_HEALTH_REPORT 270 /* R, 32 bytes */
+#define EXT_CSD_NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED 302 /* R, 4 bytes */
+ /* byte 306 is reserved */
+#define EXT_CSD_CMDQ_DEPTH 307 /* R */
+#define EXT_CSD_CMDQ_SUPPORT 308 /* R */
+ /* bytes 309-485 are reserved */
+#define EXT_CSD_BARRIER_SUPPORT 486 /* R */
+#define EXT_CSD_FFU_ARG 487 /* R, 4 bytes */
+#define EXT_CSD_OPERATION_CODE_TIMEOUT 491 /* R */
+#define EXT_CSD_FFU_FEATURES 492 /* R */
+#define EXT_CSD_SUPPORTED_MODES 493 /* R */
+#define EXT_CSD_EXT_SUPPORT 494 /* R */
+#define EXT_CSD_LARGE_UNIT_SIZE_M1 495 /* R */
+#define EXT_CSD_CONTEXT_CAPABILITIES 496 /* R */
+#define EXT_CSD_TAG_RES_SIZE 497 /* R */
+#define EXT_CSD_TAG_UNIT_SIZE 498 /* R */
+#define EXT_CSD_DATA_TAG_SUPPORT 499 /* R */
+#define EXT_CSD_MAX_PACKED_WRITES 500 /* R */
+#define EXT_CSD_MAX_PACKED_READS 501 /* R */
+#define EXT_CSD_BKOPS_SUPPORT 502 /* R */
+#define EXT_CSD_HPI_FEATURES 503 /* R */
+#define EXT_CSD_S_CMD_SET 504 /* R */
+#define EXT_CSD_EXT_SECURITY_ERR 505 /* R */
+ /* bytes 506-511 are reserved */
/*
* EXT_CSD field definitions
@@ -407,22 +574,20 @@
#define EXT_CSD_CACHE_CTRL_CACHE_EN 0x01
-#define EXT_CSD_EXT_PART_ATTR_DEFAULT 0x0
-#define EXT_CSD_EXT_PART_ATTR_SYSTEMCODE 0x1
-#define EXT_CSD_EXT_PART_ATTR_NPERSISTENT 0x2
-
-#define EXT_CSD_PART_SET_COMPLETED 0x01
+#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_DEFAULT 0x0
+#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_SYSTEMCODE 0x1
+#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_NPERSISTENT 0x2
-#define EXT_CSD_PART_ATTR_ENH_USR 0x01
-#define EXT_CSD_PART_ATTR_ENH_GP0 0x02
-#define EXT_CSD_PART_ATTR_ENH_GP1 0x04
-#define EXT_CSD_PART_ATTR_ENH_GP2 0x08
-#define EXT_CSD_PART_ATTR_ENH_GP3 0x10
-#define EXT_CSD_PART_ATTR_ENH_MASK 0x1f
+#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_USR 0x01
+#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP0 0x02
+#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP1 0x04
+#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP2 0x08
+#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP3 0x10
+#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_MASK 0x1f
-#define EXT_CSD_PART_SUPPORT_EN 0x01
-#define EXT_CSD_PART_SUPPORT_ENH_ATTR_EN 0x02
-#define EXT_CSD_PART_SUPPORT_EXT_ATTR_EN 0x04
+#define EXT_CSD_PARTITIONING_SUPPORT_EN 0x01
+#define EXT_CSD_PARTITIONING_SUPPORT_ENH_ATTR_EN 0x02
+#define EXT_CSD_PARTITIONING_SUPPORT_EXT_ATTR_EN 0x04
#define EXT_CSD_BOOT_WP_STATUS_BOOT0_PWR 0x01
#define EXT_CSD_BOOT_WP_STATUS_BOOT0_PERM 0x02
@@ -431,22 +596,22 @@
#define EXT_CSD_BOOT_WP_STATUS_BOOT1_PERM 0x08
#define EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK 0x0c
-#define EXT_CSD_ERASE_GRP_DEF_EN 0x01
-
-#define EXT_CSD_PART_CONFIG_ACC_DEFAULT 0x00
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0 0x01
-#define EXT_CSD_PART_CONFIG_ACC_BOOT1 0x02
-#define EXT_CSD_PART_CONFIG_ACC_RPMB 0x03
-#define EXT_CSD_PART_CONFIG_ACC_GP0 0x04
-#define EXT_CSD_PART_CONFIG_ACC_GP1 0x05
-#define EXT_CSD_PART_CONFIG_ACC_GP2 0x06
-#define EXT_CSD_PART_CONFIG_ACC_GP3 0x07
-#define EXT_CSD_PART_CONFIG_ACC_MASK 0x07
-#define EXT_CSD_PART_CONFIG_BOOT0 0x08
-#define EXT_CSD_PART_CONFIG_BOOT1 0x10
-#define EXT_CSD_PART_CONFIG_BOOT_USR 0x38
-#define EXT_CSD_PART_CONFIG_BOOT_MASK 0x38
-#define EXT_CSD_PART_CONFIG_BOOT_ACK 0x40
+#define EXT_CSD_ERASE_GROUP_DEF_EN 0x01
+
+#define EXT_CSD_PARTITION_CONFIG_ACC_DEFAULT 0x00
+#define EXT_CSD_PARTITION_CONFIG_ACC_BOOT0 0x01
+#define EXT_CSD_PARTITION_CONFIG_ACC_BOOT1 0x02
+#define EXT_CSD_PARTITION_CONFIG_ACC_RPMB 0x03
+#define EXT_CSD_PARTITION_CONFIG_ACC_GP0 0x04
+#define EXT_CSD_PARTITION_CONFIG_ACC_GP1 0x05
+#define EXT_CSD_PARTITION_CONFIG_ACC_GP2 0x06
+#define EXT_CSD_PARTITION_CONFIG_ACC_GP3 0x07
+#define EXT_CSD_PARTITION_CONFIG_ACC_MASK 0x07
+#define EXT_CSD_PARTITION_CONFIG_BOOT0 0x08
+#define EXT_CSD_PARTITION_CONFIG_BOOT1 0x10
+#define EXT_CSD_PARTITION_CONFIG_BOOT_USR 0x38
+#define EXT_CSD_PARTITION_CONFIG_BOOT_MASK 0x38
+#define EXT_CSD_PARTITION_CONFIG_BOOT_ACK 0x40
#define EXT_CSD_CMD_SET_NORMAL 1
#define EXT_CSD_CMD_SET_SECURE 2
@@ -463,14 +628,14 @@
#define EXT_CSD_POWER_CLASS_4BIT_MASK 0x0f
#define EXT_CSD_POWER_CLASS_4BIT_SHIFT 0
-#define EXT_CSD_CARD_TYPE_HS_26 0x0001
-#define EXT_CSD_CARD_TYPE_HS_52 0x0002
-#define EXT_CSD_CARD_TYPE_DDR_52_1_8V 0x0004
-#define EXT_CSD_CARD_TYPE_DDR_52_1_2V 0x0008
-#define EXT_CSD_CARD_TYPE_HS200_1_8V 0x0010
-#define EXT_CSD_CARD_TYPE_HS200_1_2V 0x0020
-#define EXT_CSD_CARD_TYPE_HS400_1_8V 0x0040
-#define EXT_CSD_CARD_TYPE_HS400_1_2V 0x0080
+#define EXT_CSD_DEVICE_TYPE_HS_26 0x0001
+#define EXT_CSD_DEVICE_TYPE_HS_52 0x0002
+#define EXT_CSD_DEVICE_TYPE_DDR_52_1_8V 0x0004
+#define EXT_CSD_DEVICE_TYPE_DDR_52_1_2V 0x0008
+#define EXT_CSD_DEVICE_TYPE_HS200_1_8V 0x0010
+#define EXT_CSD_DEVICE_TYPE_HS200_1_2V 0x0020
+#define EXT_CSD_DEVICE_TYPE_HS400_1_8V 0x0040
+#define EXT_CSD_DEVICE_TYPE_HS400_1_2V 0x0080
#define EXT_CSD_BUS_WIDTH_1 0
#define EXT_CSD_BUS_WIDTH_4 1
@@ -571,7 +736,7 @@
#define CCCR_CC_LSC (1 << 6)
#define SD_IO_CCCR_CISPTR 0x09 /* 0x09 - 0x0B */
-#define SD_IO_CCCR_FN0_BLKSZ 0x10 /* 0x10 - 0x11 */
+#define SD_IO_CCCR_FN0_BLKSZ 0x10 /* 0x10 - 0x11 */
#define SD_IO_CCCR_SPEED 0x13
#define CCCR_SPEED_SHS (1 << 0)
#define CCCR_SPEED_BSS_MASK (0x7 << 1)
@@ -585,10 +750,10 @@
/* Function Basic Registers (FBR) */
#define SD_IO_FBR_START 0x00100 /* Offset in F0 address space */
#define SD_IO_FBR_SIZE 0x00700 /* Total size of FBR */
-#define SD_IO_FBR_F_SIZE 0x00100 /* Size of each function */
-#define SD_IO_FBR_START_F(n) (SD_IO_FBR_START + (n-1) * SD_IO_FBR_F_SIZE)
-#define SD_IO_FBR_CIS_OFFSET 0x9 /* Offset of this function's info block within CIS area */
-#define SD_IO_FBR_IOBLKSZ 0x10 /* Block size for CMD53 block mode operations */
+#define SD_IO_FBR_F_SIZE 0x00100 /* Size of each function */
+#define SD_IO_FBR_START_F(n) (SD_IO_FBR_START + (n-1) * SD_IO_FBR_F_SIZE)
+#define SD_IO_FBR_CIS_OFFSET 0x9 /* Offset of this function's info block within CIS area */
+#define SD_IO_FBR_IOBLKSZ 0x10 /* Block size for CMD53 block mode operations */
/* Card Information Structure (CIS) */
#define SD_IO_CIS_START 0x01000 /* Offset in F0 address space */
@@ -642,6 +807,7 @@
#define MMC_OCR_MAX_VOLTAGE_SHIFT 23
#define MMC_OCR_S18R (1U << 24) /* Switching to 1.8 V requested (SD) */
#define MMC_OCR_S18A MMC_OCR_S18R /* Switching to 1.8 V accepted (SD) */
+#define MMC_OCR_2T (1U << 27) /* Version 2.0 or later Transfer (SDUC) */
#define MMC_OCR_XPC (1U << 28) /* SDXC Power Control */
#define MMC_OCR_ACCESS_MODE_BYTE (0U << 29) /* Access Mode Byte (MMC) */
#define MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */

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