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diff --git a/sys/dev/rtwn/rtl8192c/r92c_beacon.c b/sys/dev/rtwn/rtl8192c/r92c_beacon.c
--- a/sys/dev/rtwn/rtl8192c/r92c_beacon.c
+++ b/sys/dev/rtwn/rtl8192c/r92c_beacon.c
@@ -64,7 +64,6 @@
rtwn_r92c_tx_setup_macid(sc, buf, id);
txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
- txd->txdw4 |= htole32(SM(R92C_TXDW4_SEQ_SEL, id));
txd->txdw4 |= htole32(SM(R92C_TXDW4_PORT_ID, id));
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, RTWN_RIDX_CCK1));
}
diff --git a/sys/dev/rtwn/rtl8192c/r92c_tx.c b/sys/dev/rtwn/rtl8192c/r92c_tx.c
--- a/sys/dev/rtwn/rtl8192c/r92c_tx.c
+++ b/sys/dev/rtwn/rtl8192c/r92c_tx.c
@@ -272,7 +272,13 @@
if (ismcast)
txd->flags0 |= R92C_FLAGS0_BMCAST;
+ if (IEEE80211_IS_QOSDATA(wh))
+ txd->txdw4 |= htole32(R92C_TXDW4_QOS);
+
if (!ismcast) {
+ struct rtwn_node *un = RTWN_NODE(ni);
+ macid = un->id;
+
/* Unicast frame, check if an ACK is expected. */
if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
IEEE80211_QOS_ACKPOLICY_NOACK) {
@@ -281,9 +287,6 @@
maxretry));
}
- struct rtwn_node *un = RTWN_NODE(ni);
- macid = un->id;
-
if (type == IEEE80211_FC0_TYPE_DATA) {
qsel = tid % RTWN_MAX_TID;
@@ -348,7 +351,6 @@
if (!hasqos) {
/* Use HW sequence numbering for non-QoS frames. */
rtwn_r92c_tx_setup_hwseq(sc, txd);
- txd->txdw4 |= htole32(SM(R92C_TXDW4_SEQ_SEL, uvp->id));
} else {
uint16_t seqno;
@@ -409,7 +411,6 @@
if (!IEEE80211_QOS_HAS_SEQ(wh)) {
/* Use HW sequence numbering for non-QoS frames. */
rtwn_r92c_tx_setup_hwseq(sc, txd);
- txd->txdw4 |= htole32(SM(R92C_TXDW4_SEQ_SEL, uvp->id));
} else {
/* Set sequence number. */
txd->txdseq |= htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE);
@@ -438,7 +439,6 @@
if (!qos) {
rtwn_r92c_tx_setup_hwseq(sc, txd);
- txd->txdw4 |= htole32(SM(R92C_TXDW4_SEQ_SEL, id));
}
}
diff --git a/sys/dev/rtwn/rtl8192c/r92c_tx_desc.h b/sys/dev/rtwn/rtl8192c/r92c_tx_desc.h
--- a/sys/dev/rtwn/rtl8192c/r92c_tx_desc.h
+++ b/sys/dev/rtwn/rtl8192c/r92c_tx_desc.h
@@ -69,8 +69,7 @@
uint32_t txdw4;
#define R92C_TXDW4_RTSRATE_M 0x0000001f
#define R92C_TXDW4_RTSRATE_S 0
-#define R92C_TXDW4_SEQ_SEL_M 0x00000040
-#define R92C_TXDW4_SEQ_SEL_S 6
+#define R92C_TXDW4_QOS 0x00000040 /* BIT(6) for 8188cu/8192cu/8723au */
#define R92C_TXDW4_HWSEQ_EN 0x00000080
#define R92C_TXDW4_DRVRATE 0x00000100
#define R92C_TXDW4_CTS2SELF 0x00000800

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