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Index: sys/dts/arm/qcom-ipq4018-rt-ac58u.dts
===================================================================
--- sys/dts/arm/qcom-ipq4018-rt-ac58u.dts
+++ sys/dts/arm/qcom-ipq4018-rt-ac58u.dts
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-ethernet.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
Index: sys/dts/arm/qcom-ipq4019-ethernet.dtsi
===================================================================
--- /dev/null
+++ sys/dts/arm/qcom-ipq4019-ethernet.dtsi
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/net/qcom-qca807x.h>
+
+/ {
+ soc {
+ mdio: mdio@90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,ipq4019-mdio";
+ reg = <0x90000 0x64>;
+ status = "disabled";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy3: ethernet-phy@3 {
+ reg = <3>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy4: ethernet-phy@4 {
+ reg = <4>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ psgmiiphy: psgmii-phy@5 {
+ reg = <5>;
+
+ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
+ qcom,psgmii-az;
+ };
+ };
+
+ ess-switch@c000000 {
+ compatible = "qcom,ess-switch";
+ reg = <0xc000000 0x80000>;
+ switch_access_mode = "local bus";
+ resets = <&gcc ESS_RESET>;
+ reset-names = "ess_rst";
+ clocks = <&gcc GCC_ESS_CLK>;
+ clock-names = "ess_clk";
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x1e>;
+ switch_wan_bmp = <0x20>;
+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
+ switch_initvlas = <0x7c 0x54>;
+ status = "disabled";
+ };
+
+ ess-psgmii@98000 {
+ compatible = "qcom,ess-psgmii";
+ reg = <0x98000 0x800>;
+ psgmii_access_mode = "local bus";
+ status = "disabled";
+ };
+
+ edma@c080000 {
+ compatible = "qcom,ess-edma";
+ reg = <0xc080000 0x8000>;
+ qcom,page-mode = <0>;
+ qcom,rx_head_buf_size = <1540>;
+ qcom,mdio_supported;
+ qcom,poll_required = <1>;
+ qcom,num_gmac = <2>;
+ interrupts = <0 65 IRQ_TYPE_EDGE_RISING
+ 0 66 IRQ_TYPE_EDGE_RISING
+ 0 67 IRQ_TYPE_EDGE_RISING
+ 0 68 IRQ_TYPE_EDGE_RISING
+ 0 69 IRQ_TYPE_EDGE_RISING
+ 0 70 IRQ_TYPE_EDGE_RISING
+ 0 71 IRQ_TYPE_EDGE_RISING
+ 0 72 IRQ_TYPE_EDGE_RISING
+ 0 73 IRQ_TYPE_EDGE_RISING
+ 0 74 IRQ_TYPE_EDGE_RISING
+ 0 75 IRQ_TYPE_EDGE_RISING
+ 0 76 IRQ_TYPE_EDGE_RISING
+ 0 77 IRQ_TYPE_EDGE_RISING
+ 0 78 IRQ_TYPE_EDGE_RISING
+ 0 79 IRQ_TYPE_EDGE_RISING
+ 0 80 IRQ_TYPE_EDGE_RISING
+ 0 240 IRQ_TYPE_EDGE_RISING
+ 0 241 IRQ_TYPE_EDGE_RISING
+ 0 242 IRQ_TYPE_EDGE_RISING
+ 0 243 IRQ_TYPE_EDGE_RISING
+ 0 244 IRQ_TYPE_EDGE_RISING
+ 0 245 IRQ_TYPE_EDGE_RISING
+ 0 246 IRQ_TYPE_EDGE_RISING
+ 0 247 IRQ_TYPE_EDGE_RISING
+ 0 248 IRQ_TYPE_EDGE_RISING
+ 0 249 IRQ_TYPE_EDGE_RISING
+ 0 250 IRQ_TYPE_EDGE_RISING
+ 0 251 IRQ_TYPE_EDGE_RISING
+ 0 252 IRQ_TYPE_EDGE_RISING
+ 0 253 IRQ_TYPE_EDGE_RISING
+ 0 254 IRQ_TYPE_EDGE_RISING
+ 0 255 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ gmac0: gmac0 {
+ local-mac-address = [00 00 00 00 00 00];
+ vlan_tag = <1 0x1f>;
+ };
+
+ gmac1: gmac1 {
+ local-mac-address = [00 00 00 00 00 00];
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <2 0x20>;
+ };
+ };
+ };
+};
Index: sys/dts/include/dt-bindings/net/qcom-qca807x.h
===================================================================
--- /dev/null
+++ sys/dts/include/dt-bindings/net/qcom-qca807x.h
@@ -0,0 +1,81 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * DT constants for the Qualcomm QCA807x PHY
+ */
+
+#ifndef _DT_BINDINGS_NET_QCOM_QCA807X_H__
+#define _DT_BINDINGS_NET_QCOM_QCA807X_H__
+
+/*
+ * PSGMII driver configuration. This controls the TX voltage
+ * used between the SoC and the external PHY over the SERDES
+ * interface.
+ *
+ * The default value is 12 (600mV)
+ */
+#define PSGMII_QSGMII_TX_DRIVER_140MV 0
+#define PSGMII_QSGMII_TX_DRIVER_160MV 1
+#define PSGMII_QSGMII_TX_DRIVER_180MV 2
+#define PSGMII_QSGMII_TX_DRIVER_200MV 3
+#define PSGMII_QSGMII_TX_DRIVER_220MV 4
+#define PSGMII_QSGMII_TX_DRIVER_240MV 5
+#define PSGMII_QSGMII_TX_DRIVER_260MV 6
+#define PSGMII_QSGMII_TX_DRIVER_280MV 7
+#define PSGMII_QSGMII_TX_DRIVER_300MV 8
+#define PSGMII_QSGMII_TX_DRIVER_320MV 9
+#define PSGMII_QSGMII_TX_DRIVER_400MV 10
+#define PSGMII_QSGMII_TX_DRIVER_500MV 11
+#define PSGMII_QSGMII_TX_DRIVER_600MV 12
+
+/*
+ * These fields control the PHY power saving based on the
+ * cable length.
+ *
+ * 0 - full amplitude, full bias current
+ * 1 - amplitude follows cable length, half bias current
+ * 2 - full amplitude, bias current follows cable length
+ * 3 - both amplitude and bias current follow cable length
+ * 4 - full amplitude, half bias current
+ * 5 - amplitude follows cable length, 1/4 bias current
+ * when cable length < 10m else half bias current
+ * 6 - full amplitude, bias current follows cable length,
+ * bias reduced further by half when cable length < 10m
+ * 7 - amplitude follows cable length, same bias current
+ * setting as '6'
+ */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
+
+#endif /* __DT_BINDINGS_NET_QCOM_QCA807X_H__ */

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