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Index: sys/arm64/arm64/identcpu.c
===================================================================
--- sys/arm64/arm64/identcpu.c
+++ sys/arm64/arm64/identcpu.c
@@ -364,6 +364,31 @@
/* ID_AA64ISAR0_EL1 */
+static struct mrs_field_value id_aa64isar0_rndr[] = {
+ MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar0_tlb[] = {
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_IMPL, "TLBI"),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_IMPL2, "TLBI"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar0_ts[] = {
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TS_FLAGM, "CondM"),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TS_FLAGM2, "CondM-8.5"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar0_fhm[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
static struct mrs_field_value id_aa64isar0_dp[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL),
MRS_FIELD_VALUE_END,
@@ -417,6 +442,10 @@
};
static struct mrs_field id_aa64isar0_fields[] = {
+ MRS_FIELD(ID_AA64ISAR0, RNDR, false, MRS_LOWER, id_aa64isar0_rndr),
+ MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_LOWER, id_aa64isar0_tlb),
+ MRS_FIELD(ID_AA64ISAR0, TS, false, MRS_LOWER, id_aa64isar0_ts),
+ MRS_FIELD(ID_AA64ISAR0, FHM, false, MRS_LOWER, id_aa64isar0_fhm),
MRS_FIELD(ID_AA64ISAR0, DP, false, MRS_LOWER, id_aa64isar0_dp),
MRS_FIELD(ID_AA64ISAR0, SM4, false, MRS_LOWER, id_aa64isar0_sm4),
MRS_FIELD(ID_AA64ISAR0, SM3, false, MRS_LOWER, id_aa64isar0_sm3),
@@ -432,6 +461,37 @@
/* ID_AA64ISAR1_EL1 */
+static struct mrs_field_value id_aa64isar1_i8mm[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_dgh[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_bf16[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_specres[] = {
+ MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_IMPL, "PredInv"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_sb[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_frintts[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
static struct mrs_field_value id_aa64isar1_gpi[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL),
MRS_FIELD_VALUE_END,
@@ -444,6 +504,7 @@
static struct mrs_field_value id_aa64isar1_lrcpc[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LRCPC, NONE, IMPL),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_ILRCPC, "LRCPC-8.4"),
MRS_FIELD_VALUE_END,
};
@@ -463,16 +524,26 @@
};
static struct mrs_field_value id_aa64isar1_apa[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL),
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, APA, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_dpb[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DPB, NONE, IMPL),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"),
MRS_FIELD_VALUE_END,
};
static struct mrs_field id_aa64isar1_fields[] = {
+ MRS_FIELD(ID_AA64ISAR1, I8MM, false, MRS_EXACT, id_aa64isar1_i8mm),
+ MRS_FIELD(ID_AA64ISAR1, DGH, false, MRS_EXACT, id_aa64isar1_dgh),
+ MRS_FIELD(ID_AA64ISAR1, BF16, false, MRS_EXACT, id_aa64isar1_bf16),
+ MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_EXACT,
+ id_aa64isar1_specres),
+ MRS_FIELD(ID_AA64ISAR1, SB, false, MRS_EXACT, id_aa64isar1_sb),
+ MRS_FIELD(ID_AA64ISAR1, FRINTTS, false, MRS_EXACT,
+ id_aa64isar1_frintts),
MRS_FIELD(ID_AA64ISAR1, GPI, false, MRS_EXACT, id_aa64isar1_gpi),
MRS_FIELD(ID_AA64ISAR1, GPA, false, MRS_EXACT, id_aa64isar1_gpa),
MRS_FIELD(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, id_aa64isar1_lrcpc),
@@ -1168,7 +1239,7 @@
if (ID_AA64ISAR1_JSCVT_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_JSCVT_IMPL)
hwcap |= HWCAP_JSCVT;
- if (ID_AA64ISAR1_DPB_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_DPB_IMPL)
+ if (ID_AA64ISAR1_DPB_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_DPB_DCCVAP)
hwcap |= HWCAP_DCPOP;
if (ID_AA64PFR0_SVE_VAL(cpu_desc[cpu].id_aa64pfr0) == ID_AA64PFR0_SVE_IMPL)
Index: sys/arm64/include/armreg.h
===================================================================
--- sys/arm64/include/armreg.h
+++ sys/arm64/include/armreg.h
@@ -350,6 +350,28 @@
#define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK)
#define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
+#define ID_AA64ISAR0_FHM_SHIFT 48
+#define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK)
+#define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_TS_SHIFT 52
+#define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK)
+#define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS_FLAGM (UL(0x1) << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS_FLAGM2 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TLB_SHIFT 56
+#define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK)
+#define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB_IMPL (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB_IMPL2 (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_RNDR_SHIFT 60
+#define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)
+#define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK)
+#define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)
+#define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)
/* ID_AA64ISAR1_EL1 */
#define ID_AA64ISAR1_EL1 MRS_REG(3, 0, 0, 6, 1)
@@ -357,7 +379,8 @@
#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK)
#define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
-#define ID_AA64ISAR1_DPB_IMPL (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
+#define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
+#define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_APA_SHIFT 4
#define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK)
@@ -383,6 +406,7 @@
#define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
#define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC_IMPL (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_LRCPC_ILRCPC (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_GPA_SHIFT 24
#define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK)
@@ -393,6 +417,36 @@
#define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK)
#define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
+#define ID_AA64ISAR1_FRINTTS_SHIFT 32
+#define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK)
+#define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_SB_SHIFT 36
+#define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK)
+#define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SPECRES_SHIFT 40
+#define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT)
+#define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK)
+#define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT)
+#define ID_AA64ISAR1_SPECRES_IMPL (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT)
+#define ID_AA64ISAR1_BF16_SHIFT 44
+#define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT)
+#define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK)
+#define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT)
+#define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT)
+#define ID_AA64ISAR1_DGH_SHIFT 48
+#define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT)
+#define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK)
+#define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT)
+#define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT)
+#define ID_AA64ISAR1_I8MM_SHIFT 52
+#define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT)
+#define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK)
+#define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
+#define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
/* ID_AA64MMFR0_EL1 */
#define ID_AA64MMFR0_EL1 MRS_REG(3, 0, 0, 7, 0)

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