D52942.id163656.diff
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D52942.id163656.diff
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	diff --git a/sys/x86/x86/mca.c b/sys/x86/x86/mca.c
	--- a/sys/x86/x86/mca.c
	+++ b/sys/x86/x86/mca.c
	@@ -124,6 +124,17 @@
	&workaround_erratum383, 0,
	"Is the workaround for Erratum 383 on AMD Family 10h processors enabled?");

	+#ifdef DIAGNOSTIC
	+static uint64_t fake_status;
	+SYSCTL_U64(_hw_mca, OID_AUTO, fake_status, CTLFLAG_RW,
	+ &fake_status, 0,
	+ "Insert artificial MCA with given status (testing purpose only)");
	+static int fake_bank;
	+SYSCTL_INT(_hw_mca, OID_AUTO, fake_bank, CTLFLAG_RW,
	+ &fake_bank, 0,
	+ "Bank to use for artificial MCAs (testing purpose only)");
	+#endif
	+
	static STAILQ_HEAD(, mca_internal) mca_freelist;
	static int mca_freecount;
	static STAILQ_HEAD(, mca_internal) mca_records;
	@@ -701,8 +712,24 @@
	bool mce, recover;

	status = rdmsr(mca_msr_ops.status(bank));
	- if (!(status & MC_STATUS_VAL))
	+ if (!(status & MC_STATUS_VAL)) {
	+#ifdef DIAGNOSTIC
	+ /*
	+ * Check if we have a pending artificial event to generate.
	+ * Note that this is potentially racy with the sysctl. The
	+ * tradeoff is deemed acceptable given the test nature
	+ * of the code.
	+ */
	+ if (fake_status && bank == fake_bank) {
	+ status = fake_status;
	+ fake_status = 0;
	+ }
	+ if (!(status & MC_STATUS_VAL))
	+ return (0);
	+#else
	return (0);
	+#endif
	+ }

	recover = *recoverablep;
	mce = mca_is_mce(mcg_cap, status, &recover);