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D49587_additional_patch_proposal.diff
olce (Olivier Certner)
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olce
Dec 8 2025, 9:13 PM
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D49587_additional_patch_proposal.diff
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diff --git c/sys/x86/cpufreq/hwpstate_amd.c w/sys/x86/cpufreq/hwpstate_amd.c
index 08f980407e1b..deb5d0de9927 100644
--- c/sys/x86/cpufreq/hwpstate_amd.c
+++ w/sys/x86/cpufreq/hwpstate_amd.c
@@ -101,51 +101,56 @@
#define AMD_17H_CUR_DID(msr) (((msr) >> 8) & 0x3F)
#define AMD_17H_CUR_FID(msr) ((msr) & 0xFF)
#define AMD_1AH_CUR_FID(msr) ((msr) & 0xFFF)
-#define AMD_CPPC_CAPS_1_LOW_PERF(msr) ((msr >> 0) & 0xFF)
-#define AMD_CPPC_CAPS_1_LOW_NONLIN_PERF(msr) ((msr >> 8) & 0xFF)
-#define AMD_CPPC_CAPS_1_NOMINAL_PERF(msr) ((msr >> 16) & 0xFF)
-#define AMD_CPPC_CAPS_1_HIGH_PERF(msr) ((msr >> 24) & 0xFF)
+#define AMD_CPPC_CAPS_1_HIGH_PERF_BITS 0xff000000
+#define AMD_CPPC_CAPS_1_NOMINAL_PERF_BITS 0x00ff0000
+#define AMD_CPPC_CAPS_1_LOW_NONLIN_PERF_BITS 0x0000ff00
+#define AMD_CPPC_CAPS_1_LOW_PERF_BITS 0x000000ff
#define AMD_CPPC_REQUEST_ENERGY_PERF_BITS 0xff000000
#define AMD_CPPC_REQUEST_DES_PERF_BITS 0x00ff0000
#define AMD_CPPC_REQUEST_MIN_PERF_BITS 0x0000ff00
#define AMD_CPPC_REQUEST_MAX_PERF_BITS 0x000000ff
+#define BITS_VALUE(bits, num) (((num) & (bits)) >> (ffsll((bits)) - 1))
+#define BITS_WITH_VALUE(bits, val) ((uintmax_t)(val) << (ffsll((bits)) - 1))
+#define SET_BITS_VALUE(var, bits, val) \
+ ((var) = (var) & ~(bits) | BITS_WITH_VALUE((bits), (val)))
+
#define HWPSTATE_DEBUG(dev, msg...) \
do { \
if (hwpstate_verbose) \
device_printf(dev, msg); \
} while (0)
struct hwpstate_setting {
int freq; /* CPU clock in Mhz or 100ths of a percent. */
int volts; /* Voltage in mV. */
int power; /* Power consumed in mW. */
int lat; /* Transition latency in us. */
int pstate_id; /* P-State id */
};
-struct hwpstate_cppc_setting {
+struct hwpstate_cppc_state {
uint8_t high;
uint8_t guaranteed;
uint8_t efficient;
uint8_t low;
};
enum hwpstate_flags {
PSTATE_CPPC = 1,
};
struct hwpstate_softc {
device_t dev;
union {
struct hwpstate_setting
hwpstate_settings[AMD_10H_11H_MAX_STATES];
- struct hwpstate_cppc_setting cppc_settings;
+ struct hwpstate_cppc_state cppc_state;
};
int cfnum;
uint32_t flags;
uint64_t req;
};
@@ -234,17 +239,17 @@ amdhwp_dump_sysctl_handler(SYSCTL_HANDLER_ARGS)
goto out;
}
rdmsr_safe(MSR_AMD_CPPC_CAPS_1, &data);
sbuf_printf(sb, "\tHighest Performance: %03ju\n",
- AMD_CPPC_CAPS_1_HIGH_PERF(data));
+ BITS_VALUE(AMD_CPPC_CAPS_1_HIGH_PERF_BITS, data));
sbuf_printf(sb, "\tGuaranteed Performance: %03ju\n",
- AMD_CPPC_CAPS_1_NOMINAL_PERF(data));
+ BITS_VALUE(AMD_CPPC_CAPS_1_NOMINAL_PERF_BITS, data));
sbuf_printf(sb, "\tEfficient Performance: %03ju\n",
- AMD_CPPC_CAPS_1_LOW_NONLIN_PERF(data));
+ BITS_VALUE(AMD_CPPC_CAPS_1_LOW_NONLIN_PERF_BITS, data));
sbuf_printf(sb, "\tLowest Performance: %03ju\n",
- AMD_CPPC_CAPS_1_LOW_PERF(data));
+ BITS_VALUE(AMD_CPPC_CAPS_1_LOW_PERF_BITS, data));
sbuf_putc(sb, '\n');
rdmsr_safe(MSR_AMD_CPPC_REQUEST, &data);
#define pkg_print(name, offset) \
@@ -278,50 +283,48 @@ static int
sysctl_epp_select(SYSCTL_HANDLER_ARGS)
{
device_t dev;
struct hwpstate_softc *sc;
struct pcpu *pc;
+ uint64_t r;
+ const uint32_t max_energy_perf = BITS_VALUE(
+ AMD_CPPC_REQUEST_ENERGY_PERF_BITS, (uint64_t)-1);
uint32_t val;
int ret = 0;
int i, cpu;
- uint64_t r;
dev = oidp->oid_arg1;
sc = device_get_softc(dev);
if (!(sc->flags & PSTATE_CPPC))
return (ENODEV);
pc = cpu_get_pcpu(dev);
if (pc == NULL)
return (ENXIO);
- val = ((sc->req & AMD_CPPC_REQUEST_ENERGY_PERF_BITS) >>
- (ffsll(AMD_CPPC_REQUEST_ENERGY_PERF_BITS) - 1)) *
- 100 / 0xFF;
+ val = BITS_VALUE(AMD_CPPC_REQUEST_ENERGY_PERF_BITS, sc->req) * 100 /
+ max_energy_perf;
ret = sysctl_handle_int(oidp, &val, 0, req);
if (ret || req->newptr == NULL)
goto end;
if (val > 100) {
ret = EINVAL;
goto end;
}
- val = (val * 0xFF) / 100;
+ val = (val * max_energy_perf) / 100;
thread_lock(curthread);
sched_bind(curthread, pc->pc_cpuid);
thread_unlock(curthread);
ret = rdmsr_safe(MSR_AMD_CPPC_REQUEST, &sc->req);
if (ret)
goto end;
cpu = pc->pc_cpuid;
r = sc->req;
- r = r & ~AMD_CPPC_REQUEST_ENERGY_PERF_BITS;
- r |= (val & 0xFFULL) << (ffsll(AMD_CPPC_REQUEST_ENERGY_PERF_BITS) - 1);
- if (r == sc->req)
- goto end;
+ SET_BITS_VALUE(r, AMD_CPPC_REQUEST_ENERGY_PERF_BITS, val);
ret = wrmsr_safe(MSR_AMD_CPPC_REQUEST, r);
if (ret)
goto end;
thread_lock(curthread);
@@ -623,29 +626,31 @@ amd_set_autonomous_hwp(struct hwpstate_softc *sc)
device_printf(dev,
"Failed to read HWP capabilities MSR for cpu%d (%d)\n",
pc->pc_cpuid, ret);
goto out;
}
- sc->cppc_settings.high = AMD_CPPC_CAPS_1_HIGH_PERF(caps);
- sc->cppc_settings.guaranteed = AMD_CPPC_CAPS_1_NOMINAL_PERF(caps);
- sc->cppc_settings.efficient = AMD_CPPC_CAPS_1_LOW_NONLIN_PERF(caps);
- sc->cppc_settings.low = AMD_CPPC_CAPS_1_LOW_PERF(caps);
+ sc->cppc_state.high = BITS_VALUE(
+ AMD_CPPC_CAPS_1_HIGH_PERF_BITS, caps);
+ sc->cppc_state.guaranteed = BITS_VALUE(
+ AMD_CPPC_CAPS_1_NOMINAL_PERF_BITS, caps);
+ sc->cppc_state.efficient = BITS_VALUE(
+ AMD_CPPC_CAPS_1_LOW_NONLIN_PERF_BITS, caps);
+ sc->cppc_state.low = BITS_VALUE(
+ AMD_CPPC_CAPS_1_LOW_PERF_BITS, caps);
- /* enable autonomous mode by setting desired performance to 0 */
- sc->req &= ~AMD_CPPC_REQUEST_DES_PERF_BITS;
-#define SET_VALUES(val, BITS) \
- sc->req = (sc->req & ~(BITS)) | \
- (((uint32_t)(val) & 0xFF) << (ffsll((BITS)) - 1))
/*
- * In intel's reference, the default value of EPP is 0x80u which is the
- * balanced mode. For consistency, we set the same value in AMD's CPPC
- * driver.
+ * In Intel's reference manual, the default value of EPP is 0x80u which
+ * is the balanced mode. For consistency, we set the same value in AMD's
+ * CPPC driver.
*/
- SET_VALUES(0x80U, AMD_CPPC_REQUEST_ENERGY_PERF_BITS);
- SET_VALUES(sc->cppc_settings.low, AMD_CPPC_REQUEST_MIN_PERF_BITS);
- SET_VALUES(sc->cppc_settings.high, AMD_CPPC_REQUEST_MAX_PERF_BITS);
-#undef SET_VALUES
+ SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_ENERGY_PERF_BITS, 0x80);
+ SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_MIN_PERF_BITS,
+ sc->cppc_state.low);
+ SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_MAX_PERF_BITS,
+ sc->cppc_state.high);
+ /* enable autonomous mode by setting desired performance to 0 */
+ SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_DES_PERF_BITS, 0);
ret = wrmsr_safe(MSR_AMD_CPPC_REQUEST, sc->req);
if (ret) {
device_printf(dev,
"Failed to setup autonomous HWP for cpu%d\n",

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