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D12268.id32795.diff
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Index: sys/x86/pci/qpi.c
===================================================================
--- sys/x86/pci/qpi.c
+++ sys/x86/pci/qpi.c
@@ -63,11 +63,17 @@
static void
qpi_identify(driver_t *driver, device_t parent)
{
+ int do_qpi;
/* Check CPUID to ensure this is an i7 CPU of some sort. */
- if (!(cpu_vendor_id == CPU_VENDOR_INTEL &&
- CPUID_TO_FAMILY(cpu_id) == 0x6 &&
- (CPUID_TO_MODEL(cpu_id) == 0x1a || CPUID_TO_MODEL(cpu_id) == 0x2c)))
+ if (cpu_vendor_id != CPU_VENDOR_INTEL ||
+ CPUID_TO_FAMILY(cpu_id) != 0x6)
+ return;
+
+ /* Only discover buses with configuration devices if allowed by user */
+ do_qpi = 0;
+ TUNABLE_INT_FETCH("hw.attach_intel_csr_pci", &do_qpi);
+ if (!do_qpi)
return;
/* PCI config register access is required. */
@@ -97,6 +103,7 @@
struct qpi_device *qdev;
device_t child;
uint32_t devid;
+ int s;
/*
* If a PCI bus already exists for this bus number, then
@@ -110,14 +117,19 @@
* the bus. A value of 0xffffffff means that the bus is not
* present.
*/
- devid = pci_cfgregread(bus, 0, 0, PCIR_DEVVENDOR, 4);
+ for (s = 0; s < 0x20; s++) {
+ devid = pci_cfgregread(bus, s, 0, PCIR_DEVVENDOR, 4);
+ if (devid != 0xffffffff)
+ break;
+ }
if (devid == 0xffffffff)
return (ENOENT);
if ((devid & 0xffff) != 0x8086) {
- device_printf(dev,
- "Device at pci%d.0.0 has non-Intel vendor 0x%x\n", bus,
- devid & 0xffff);
+ if (bootverbose)
+ device_printf(dev,
+ "Device at pci%d.%d.0 has non-Intel vendor 0x%x\n",
+ bus, s, devid & 0xffff);
return (ENXIO);
}
@@ -137,12 +149,12 @@
int bus;
/*
- * Each processor socket has a dedicated PCI bus counting down from
- * 255. We keep probing buses until one fails.
+ * Each processor socket has a dedicated PCI bus, sometimes
+ * not enumerated by ACPI. Probe all unattached buses from 0
+ * to 255.
*/
- for (bus = 255;; bus--)
- if (qpi_probe_pcib(dev, bus) != 0)
- break;
+ for (bus = 255; bus >= 0; bus--)
+ qpi_probe_pcib(dev, bus);
return (bus_generic_attach(dev));
}
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D12268: Enhance qpi.c to make it usable on all Core-microarchitecture Xeons.
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