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Index: head/lib/libc/arm/Symbol.map
===================================================================
--- head/lib/libc/arm/Symbol.map
+++ head/lib/libc/arm/Symbol.map
@@ -41,6 +41,11 @@
dl_unwind_find_exidx;
};
+FBSD_1.6 {
+ arm_drain_writebuf;
+ arm_sync_icache;
+};
+
FBSDprivate_1.0 {
/* PSEUDO syscalls */
_getlogin;
Index: head/lib/libc/arm/gen/Makefile.inc
===================================================================
--- head/lib/libc/arm/gen/Makefile.inc
+++ head/lib/libc/arm/gen/Makefile.inc
@@ -8,6 +8,8 @@
_setjmp.S \
alloca.S \
arm_initfini.c \
+ arm_drain_writebuf.c \
+ arm_sync_icache.c \
fabs.c \
flt_rounds.c \
getcontextx.c \
@@ -17,6 +19,10 @@
setjmp.S \
signalcontext.c \
sigsetjmp.S \
+
+MAN+= \
+ arm_drain_writebuf.2 \
+ arm_sync_icache.2 \
.if ${MACHINE_ARCH:Marmv[67]*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "")
Index: head/lib/libc/arm/gen/arm_drain_writebuf.2
===================================================================
--- head/lib/libc/arm/gen/arm_drain_writebuf.2
+++ head/lib/libc/arm/gen/arm_drain_writebuf.2
@@ -0,0 +1,77 @@
+.\" Copyright (c) 2019 Ian Lepore <ian@FreeBSD.org>
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd July 10, 2019
+.Dt ARM_DRAIN_WRITEBUF 2
+.Os
+.Sh NAME
+.Nm arm_drain_writebuf
+.Nd drain pending writes from cores and caches
+.Sh LIBRARY
+.Lb libc
+.Sh SYNOPSIS
+.In machine/sysarch.h
+.Ft int
+.Fn arm_drain_writebuf void
+.Sh DESCRIPTION
+The
+.Nm
+system call causes all pending writes from ARM cores and caches to be
+written out to main memory or memory-mapped I/O registers.
+Not all hardware supports buffered writes; on such systems the
+.Nm
+function is a no-op.
+.Pp
+On ARMv5 systems, this executes a cp15 coprocessor
+.Dq drain write buffer
+operation.
+On ARMv6 and ARMv7 systems, this executes a
+.Dq DSB SY
+synchronization barrier, followed by an L2 cache drain on
+systems where the DSB does not include L2 automatically.
+.Pp
+.Nm
+attempts to wait for the drain operation to complete, but cannot
+guarantee the writes have reached their ultimate destination on all hardware.
+For example, on an ARMv7 system,
+.Nm
+tells the L2 cache controller to drain its buffers, and it waits until
+the controller indicates that operation is complete.
+However, all the L2 controller knows is that the data was accepted for
+delivery by the AXI bus.
+If the ultimate destination of the write is a device on a subordinate
+bus connected to the AXI bus, more buffering or other delays may occur
+on that subordinate bus.
+The only way to be certain a pending write has reached its
+ultimate destination is to issue a read from that destination after
+.Nm
+returns.
+.Sh RETURN VALUES
+The
+.Nm
+system call cannot fail, and always returns 0.
+.Sh AUTHORS
+This man page was written by
+.An Ian Lepore .
Index: head/lib/libc/arm/gen/arm_drain_writebuf.c
===================================================================
--- head/lib/libc/arm/gen/arm_drain_writebuf.c
+++ head/lib/libc/arm/gen/arm_drain_writebuf.c
@@ -0,0 +1,39 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ian Lepore <ian@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <machine/sysarch.h>
+#include <stddef.h>
+
+int
+arm_drain_writebuf(void)
+{
+ sysarch(ARM_DRAIN_WRITEBUF, NULL);
+ return (0);
+}
Index: head/lib/libc/arm/gen/arm_sync_icache.2
===================================================================
--- head/lib/libc/arm/gen/arm_sync_icache.2
+++ head/lib/libc/arm/gen/arm_sync_icache.2
@@ -0,0 +1,79 @@
+.\" Copyright (c) 2019 Ian Lepore <ian@FreeBSD.org>
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd July 10, 2019
+.Dt ARM_sync_icache 2
+.Os
+.Sh NAME
+.Nm arm_sync_icache
+.Nd synchronize the data and instruction caches
+.Sh LIBRARY
+.Lb libc
+.Sh SYNOPSIS
+.In machine/sysarch.h
+.Ft int
+.Fn arm_sync_icache "u_int addr" "int len"
+.Sh DESCRIPTION
+The
+.Nm
+system call synchronizes the contents of any data and instructions caches
+with the contents of main memory for the given range.
+Use this after loading executable code or modifying existing code in memory,
+before attempting to execute that code.
+.Pp
+The
+.Va addr
+and
+.Va len
+arguments do not need to be aligned to any particular boundary, but
+cache operations will affect entire cache lines, even those which are only
+partially overlapped by the given range.
+.Pp
+This takes one or more of the following actions, depending on the requirements
+of the hardware:
+.Bl -bullet
+.It
+Write dirty data cache lines within the range back to main memory.
+.It
+Invalidate existing instruction cache contents for the range.
+.It
+Invalidate branch prediction caches for the range.
+.El
+.Pp
+On hardware which supports multiple synchronization points for cache
+operations, the caches are maintained to the point of unification,
+making the data in the range coherent amongst all cores.
+.Sh RETURN VALUES
+The
+.Nm
+system call always returns 0.
+.Sh ERRORS
+If a call refers to memory which the calling process does not have rights
+to access, or if the
+.Va len
+argument is negative, a SIGSEGV signal is delivered to the calling thread.
+.Sh AUTHORS
+This man page was written by
+.An Ian Lepore .
Index: head/lib/libc/arm/gen/arm_sync_icache.c
===================================================================
--- head/lib/libc/arm/gen/arm_sync_icache.c
+++ head/lib/libc/arm/gen/arm_sync_icache.c
@@ -0,0 +1,44 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ian Lepore <ian@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/types.h>
+#include <machine/sysarch.h>
+#include <stddef.h>
+
+int
+arm_sync_icache(u_int addr, int len)
+{
+ struct arm_sync_icache_args args;
+
+ args.addr = addr;
+ args.len = len;
+ sysarch(ARM_SYNC_ICACHE, &args);
+ return (0);
+}
Index: head/sys/sys/param.h
===================================================================
--- head/sys/sys/param.h
+++ head/sys/sys/param.h
@@ -60,7 +60,7 @@
* in the range 5 to 9.
*/
#undef __FreeBSD_version
-#define __FreeBSD_version 1300035 /* Master, propagated to newvers */
+#define __FreeBSD_version 1300036 /* Master, propagated to newvers */
/*
* __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD,

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