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Index: head/sys/powerpc/booke/machdep_e500.c
===================================================================
--- head/sys/powerpc/booke/machdep_e500.c
+++ head/sys/powerpc/booke/machdep_e500.c
@@ -91,7 +91,17 @@
if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
(((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
csr = mfspr(SPR_L2CSR0);
- if ((csr & L2CSR0_L2E) == 0) {
+ /*
+ * Don't actually attempt to manipulate the L2 cache if
+ * L2CFG0 is zero.
+ *
+ * Any chip with a working L2 cache will have a nonzero
+ * L2CFG0, as it will have a nonzero L2CSIZE field.
+ *
+ * This fixes waiting forever for cache enable in qemu,
+ * which does not implement the L2 cache.
+ */
+ if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) {
l2cache_inval();
l2cache_enable();
}
Index: head/sys/powerpc/include/spr.h
===================================================================
--- head/sys/powerpc/include/spr.h
+++ head/sys/powerpc/include/spr.h
@@ -887,6 +887,7 @@
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
+#define SPR_L2CFG0 0x207 /* ..8 L2 Configuration Register 0 */
#define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */

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