D41816.diff
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	diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
	--- a/sys/amd64/amd64/initcpu.c
	+++ b/sys/amd64/amd64/initcpu.c
	@@ -101,7 +101,8 @@
	case 0x10:
	case 0x12:
	if ((cpu_feature2 & CPUID2_HV) == 0)
	- wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) \| 1);
	+ wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) \|
	+ DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT);
	break;
	}

	@@ -151,7 +152,7 @@
	(cpu_feature2 & CPUID2_HV) == 0) {
	/* 1021 */
	msr = rdmsr(MSR_DE_CFG);
	- msr \|= 0x2000;
	+ msr \|= DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT;
	wrmsr(MSR_DE_CFG, msr);

	/* 1033 */
	diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h
	--- a/sys/x86/include/specialreg.h
	+++ b/sys/x86/include/specialreg.h
	@@ -1162,11 +1162,16 @@
	#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
	#define MSR_DE_CFG 0xc0011029 /* Decode Configuration */

	+/* MSR_AMDK8_IPM */
	+#define AMDK8_SMIONCMPHALT (1ULL << 27)
	+#define AMDK8_C1EONCMPHALT (1ULL << 28)
	+
	/* MSR_VM_CR related */
	#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */

	-#define AMDK8_SMIONCMPHALT (1ULL << 27)
	-#define AMDK8_C1EONCMPHALT (1ULL << 28)
	+/* MSR_DE_CFG */
	+#define DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT 0x1
	+#define DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT 0x2000

	/* VIA ACE crypto featureset: for via_feature_rng */
	#define VIA_HAS_RNG 1 /* cpu has RNG */