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[MIPS] Print Config7 on boot for several MIPS architectures
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Authored by mizhka on Nov 14 2016, 8:13 PM.

Details

Summary

Hi,

Config7 contains useful fields, for instance, field AR indicating that the D-cache is configured to avoid cache aliases. This patch brings printing of config7 for MIPS 24K, 74K, 1004K.

Test Plan

Tested on MIPS74k (BCM5358).

Testing on 1004K and 24K are needed/welcome!

Diff Detail

Repository
rS FreeBSD src repository
Lint
Automatic diff as part of commit; lint not applicable.
Unit
Automatic diff as part of commit; unit tests not applicable.

Event Timeline

mizhka retitled this revision from to [MIPS] Print Config7 on boot for several MIPS architectures.Nov 14 2016, 8:13 PM
mizhka updated this object.
mizhka edited the test plan for this revision. (Show Details)
mizhka added a reviewer: adrian.
mizhka set the repository for this revision to rS FreeBSD src repository.
mizhka updated this revision to Diff 22197.
imp added inline comments.Nov 14 2016, 8:14 PM
sys/mips/mips/cpu.c
483 ↗(On Diff #22197)

I thought there was a config register that said cp7 was valid. Shouldn't we be checking that rather than this long list of #fidefs?

adrian edited edge metadata.Nov 14 2016, 8:21 PM
adrian accepted this revision.

can you also decode the other config7 bits? eg for mips24k:

Config7[WII]: Read-only bit which tells you how wait behaves. When this bit is set, an interrupt which would occur
just so long as Status[IE] is set 1 will always be enough to terminate a wait instruction.
24K family CPUs where WII reads 0 will remain in the wait condition forever if entered with interrupts disabled.

Is that the same on mips74k? (WII == bit31)

sys/mips/mips/cpu.c
483 ↗(On Diff #22197)

not on mips24k/mips74k.

This revision is now accepted and ready to land.Nov 14 2016, 8:21 PM
mizhka added inline comments.Nov 14 2016, 8:21 PM
sys/mips/mips/cpu.c
483 ↗(On Diff #22197)

There is no bit to identify CP7 presence. Generic MIPS32 Architecture guide mentions only Config1-5. And only 1004k/24k/74k docs mention Config7 as "Config7 register contains implementation specific configuration information. A number of these bits are write-able to disable certain performance enhancing features within the CPU").

adrian added inline comments.Nov 14 2016, 9:16 PM
sys/mips/mips/cpu.c
339 ↗(On Diff #22197)

unused cfg7 if we don't have a cpu that uses it.

mizhka updated this object.Nov 14 2016, 9:31 PM
mizhka edited the test plan for this revision. (Show Details)
mizhka edited edge metadata.
mizhka updated this revision to Diff 22199.
This revision now requires review to proceed.Nov 14 2016, 9:31 PM
adrian edited edge metadata.Nov 14 2016, 9:32 PM
adrian accepted this revision.
This revision is now accepted and ready to land.Nov 14 2016, 9:32 PM
This revision was automatically updated to reflect the committed changes.