cad/hs-verismith: Improve port

[alven]

Summary

• Switch upstream to Hackage
• Improve COMMENT and pkg-descr

Test Plan

For every {151amd64, 144amd64}:

• Successful poudriere testport
• Successful run-testing

[yuri]

Thanks Älven for this patch!

Approved.

As an aside:
I tried to use Verismith a few years ago when I needed a lot of random Verilog testcases.
Results were disappointing: produced Verilog had a lot of errors, and Verilog programs that it was generating were too similar to each other.
There was not enough variety and non-random parts needed to be present which they weren't.
Back then I was planning to write my own Verilog generator but then this project has faded and life moved on to other things ....