Fix PIC IRR handling for level-triggered pins.

[neel]

Summary

For level triggered interrupts clear the PIC IRR bit when the interrupt pin
is deasserted. Prior to this change each assertion on a level triggered irq
pin resulted in two interrupts being delivered to the CPU.

Test Plan

Boot a FreeBSD/i386 guest with 'hint.apic.0.disabled=1' set in the loader.

root@b386:~ # uname -a
FreeBSD b386 10.0-RELEASE FreeBSD 10.0-RELEASE #5: Tue Aug 19 14:32:17 PDT 2014 root@b386:/usr/obj/usr/src/sys/GENERIC i386

Before this change:

vmstat -i

interrupt total rate
irq6: virtio_pci1 2226 222

root@b386:~ # find / > /dev/null # trigger virtio-blk interrupts

vmstat -i

interrupt total rate
irq6: virtio_pci1 24822 1460

Delta is 22596 interrupts

After the change:

vmstat -i

interrupt total rate
irq6: virtio_pci1 1108 123

root@b386:~ # find / > /dev/null # trigger virtio-blk interrupts

vmstat -i

interrupt total rate
irq6: virtio_pci1 12408 653

Delta is 11300 interrupts

[tychon]

Looks good to me.