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- Oct 6 2016, 10:35 AM (397 w, 2 d)
Jul 25 2017
Hi, any comments to the patch?
Jun 21 2017
Do not add redundant 'dma-coherent', and add the property only for the PL310 node. Unlike linux, we do not have to do it in runtime, hacking the platform code.
- Modify nexus dma tag, following https://reviews.freebsd.org/D11202
- Improve commit log
- Change ddr_attr for A38x SoCs, depending on the compatible string in the ofwbus ("/")
Extract @ian 's changes around nexus and modify the commit log.
Need to take over the revision for the patch update.
Correct comments in the code, pointed by @ian
Jun 20 2017
Hi @ian we cleaned the code a bit, solution seems nice, but... bus_dma_tag_create() won't work in platform_late_init stage, because it uses malloc :/ I have some hacks in mind how to overcome it, e.g. create the default dma tag in nexus code only when nexus_set_dma_tag() is called. The caller would only pass the desired flag and trigger tag creation inside nexus. What do you think?
Jun 19 2017
@ian thank - I'll test and let know.
Jun 17 2017
Improve checking the "arm,io-coherent" property as pointed by @meloun-miracle-cz
I checked, and indeed r320054 fixes problems with obtaing the variables, so this patch is no longer needed.
Add "arm,io-coherent" to PL310 node (see https://reviews.freebsd.org/D11245)
Do not remove cpufuncs.cf_l2cache_drain_writebuf, due to introducing "arm,io-coherent" property for PL310 in https://reviews.freebsd.org/D11245
Jun 16 2017
Tested on Armada 388 Clearfog
Tested on Armada 38x
Jun 15 2017
Yes, it's all documented in Marvell errata for the support. Both their private and the mainline kernels had to be modified in a similar way. Just please take a look:
https://patchwork.kernel.org/patch/6993601/
Jun 14 2017
Instead of using weak_reference for get_cpu_clk, provide dummy functions for all other Marvell SoC's (same way as get_tclk is done).
Indeed, but what you propose (remove cpu_class check for ARMv7), was done in the first version of this patch - briefly rejected.
Jun 11 2017
Commited to revision 319706
Jun 8 2017
- correct style for all #define and other style(9) fixes
- remove magics
- enable dynamic coherency settings detection instead of option config
- remove SoC ifdefs in mv_common and use custom setup/dump routines for neta
- enable setting MVNETA_MULTIQUEUE and MVNETA_KTR as a config option
- optimize DELAY usage in busy wait loops in miibus methods
- add missing resources free on error in init
- remove HWCSUM_IPV6 ifdefs
- replace fdt_find_compatible with ofw_bus_find_compatible
Replace magic number with macro, as pointed by @bz
Instead of removing cpu_class check in hwpmc, enable its usage amoung ARMv6/v7 SoCs.
Jun 7 2017
Hi @meloun-miracle-cz and @andrew
Jun 3 2017
May 25 2017
GL3224 is a dual LUN, but fails to report them properly - the outcome without quirks are errors and undetected devices, connected to it.
Thanks for a brief response. It happened on various Marvell Armada 38x boards + different AR983x cards. With this small fix all init problems were gone.
May 19 2017
Switched to nitems, thanks for the suggestion.
May 18 2017
The issue was already fixed on HEAD in r312746
May 17 2017
Thanks, I've just prepared a patch rebased against your change - it has slightly improved if statements. Verified with the network traffic.
May 16 2017
Thanks for the suggestion. It works, so I'll the patch in a moment.
May 14 2017
May 10 2017
May 9 2017
May 5 2017
May 4 2017
Would it be possible that you commit change pointed by zbb?
https://github.com/strejda/tegra/commit/3b5138751ee5643992b20fcb21b280fab433bb20
Apr 19 2017
Apr 11 2017
Ok, checked - Armada38x comprises r3p3 cache controller revision. I'm uploading second version of the patch, which adds missing condition checks for PL310_ERRATA_727915.
Here's an explanation from gber, who is the commit author:
If my understanding of code responsible for initial mapping is correct, then all the memory reserved from kernel space by pmap_alloc_specials() function called in pmap_bootstrap() should be mapped initially by initarm(). To create initial mapping initarm() function reserves proper number of l2 page tables. However the number of the l2 page tables does not take into account memory for: pmap_kernel_l2ptp_kva, pmap_kernel_l2dtable_kva, crashdumpmap, etc.
Apr 1 2017
Ok, agree, the ifdef is not nice. Thank you for the hint, I'll try it.
Thanks. I'll confirm this and either abandon this patch or get back with something cleaner.
Mar 31 2017
Does GENERIC kernel support Armada 38x SoC? If not, is this really an issue here?