Change Details

T-HEAD CPUs provide a spec-violating implementation of page-based memory types, using PTE bits [63:59]. Aside from the philosophical problems with this approach, the reality of increasing availability of T-HEAD platforms which implement this means that we need to consider adapting to this. Add support for this "errata". There is still quite a bit of refinement needed, as well as testing. Note that this change is not enough on its own, but some workaround will be needed for the bootstrap (locore) page tables as well.

T-HEAD CPUs provide a spec-violating implementation of page-based memory types, using PTE bits [63:59]. Add basic support for this "errata", referred to in some places as an "extension". Note that this change is not enough on its own, but a workaround is needed for the bootstrap (locore) page tables as well.

T-HEAD CPUs provide a spec-violating implementation of page-based memory types, using PTE bits [63:59]. Aside from the philosophical problemsAdd basic support for this "errata", with this approach, the reality of increasing availability of T-HEAD platforms which implement this means that we need to consider adapting to thisreferred to in some places as an "extension". Add support for this "errata".Note that this change is not enough on its own, There is still quite a bit of refinementbut a workaround is needed, as well as testing. Note that this change is not enough on its for the bootstrap (locore) page tables as well. own, but some workaround will be needed for the bootstrap (locore) page tables as well.