Change Details

I have booted this with the qemu "sifive_u" platform, and dmesg shows that the clocks are registered. I would prefer this set of changes be tested on a real SiFive Unleashed though. Sysctl output showing the new PLLs: ``` dev.fu540prci.0.clocks: coreclk ddrclk gemgxclk tlclk ```

I have booted this with the qemu "sifive_u" platform, and dmesg shows that the clocks are registered. I would prefer this set of changes be tested on a real SiFive Unleashed though. Sysctl output showing the new PLLs: ``` dev.fu540prci.0.clocks: coreclk ddrclk gemgxclk tlclk ... hw.clock.gemgxclk.enable_cnt: 0 hw.clock.gemgxclk.childrens: hw.clock.gemgxclk.parents: hfclk rtcclk hw.clock.gemgxclk.parent: hfclk hw.clock.gemgxclk.frequency: 0 hw.clock.ddrclk.enable_cnt: 0 hw.clock.ddrclk.childrens: hw.clock.ddrclk.parents: hfclk rtcclk hw.clock.ddrclk.parent: hfclk hw.clock.ddrclk.frequency: 0 ```

I have booted this with the qemu "sifive_u" platform, and dmesg shows that the clocks are registered. I would prefer this set of changes be tested on a real SiFive Unleashed though. Sysctl output showing the new PLLs: ``` dev.fu540prci.0.clocks: coreclk ddrclk gemgxclk tlclk ... hw.clock.gemgxclk.enable_cnt: 0 hw.clock.gemgxclk.childrens: hw.clock.gemgxclk.parents: hfclk rtcclk hw.clock.gemgxclk.parent: hfclk hw.clock.gemgxclk.frequency: 0 hw.clock.ddrclk.enable_cnt: 0 hw.clock.ddrclk.childrens: hw.clock.ddrclk.parents: hfclk rtcclk hw.clock.ddrclk.parent: hfclk hw.clock.ddrclk.frequency: 0 ```