Change Details

The parentheses being in the wrong place means that, for L3 pages, oldpte has all bits except PTE_V cleared, and so all the subsequent checks against oldpte will fail, causing us to bail out and not retry the faulting instruction after an SFENCE.VMA. This caused a WITNESS + INVARIANTS kernel to fault on the "Chisel P3" (BOOM-based) DARPA SSITH GFE SoC in pmap_init when writing to pv_table and, being a nofault entry, subsequently panic with: panic: vm_fault_lookup: fault on nofault entry, addr: 0xffffffc004e00000

The parentheses being in the wrong place means that, for L3 pages, oldpte has all bits except PTE_V cleared, and so all the subsequent checks against oldpte will fail, causing us to bail out and not retry the faulting instruction after an SFENCE.VMA. This causes a WITNESS + INVARIANTS kernel to fault on the "Chisel P3" (BOOM-based) DARPA SSITH GFE SoC in pmap_init when writing to pv_table and, being a nofault entry, subsequently panic with: panic: vm_fault_lookup: fault on nofault entry, addr: 0xffffffc004e00000

The parentheses being in the wrong place means that, for L3 pages, oldpte has all bits except PTE_V cleared, and so all the subsequent checks against oldpte will fail, causing us to bail out and not retry the faulting instruction after an SFENCE.VMA. This causeds a WITNESS + INVARIANTS kernel to fault on the "Chisel P3" (BOOM-based) DARPA SSITH GFE SoC in pmap_init when writing to pv_table and, being a nofault entry, subsequently panic with: panic: vm_fault_lookup: fault on nofault entry, addr: 0xffffffc004e00000