Change Details

When allocating an interrupt that is routed through the CP110 we need to create a mapping between it and the parent interrupt controller. Before this patch we relied on it being done in firmware. This worked with EDK2 and older versions of u-boot, but in the newer ones the mapping is no longer done there. With this patch irq number is allocated in GICP/SEI and passed down to ICU which does the mapping. This allows us to boot on armada 7k/8k boards that run modern uboot. For SATA interrupts we need to apply a WA previously done in firmware. We have two SATA ports connected to one controller. Each ports gets its own interrupt, but only one of them is described in dts, also ahci_generic driver expects only one irq per controller. Fix it by mapping both CP110 interrupts when one of them is allocated. This way the same irq is triggered in GICP when either port fires an interrupt. In the case of SEI we have two types of interrupts - ones that are directly connected to AP806 and others that are routed through CP110. The former require 1:1 mapping, the latter are handled in the same way as interrupts in GICP.

On Armada8k boards various peripherals (e.g. USB) have interrupt lines connected to on of the ICU interrupt controllers. After an interrupt is detected it triggers MSI to a given address, with a programmed value. This in turn triggers an SPI interrupt. Normally MSI vector should be allocated by ICUs parent and set during interrupt allocation. Instead of doing that we relied on the ICU being pre-configured in firmware. This worked with EDK2 and older versions of u-boot, but in the newer ones that is no longer the case. Extend ICU msi-parents - GICP and SEI to support MSI interface and use it during interrupt allocation. This allows us to boot on armada 7k/8k SoCs that run modern uboot. For SATA interrupts we need to apply a WA previously done in firmware. We have two SATA ports connected to one controller. Each ports gets its own interrupt, but only one of them is described in dts, also ahci_generic driver expects only one irq too. Fix it by mapping both interrupts to the same MSI when one of them is allocated, which allows us to use both SATA ports.

When allocating an interrupt that is routed through the CP110 we need to create a mapping between it and the parent interrupt controllerOn Armada8k boards various peripherals (e.g. USB) have interrupt lines connected to on of the ICU interrupt controllers. Before this patch we relied on it being done in firmwareAfter an interrupt is detected it triggers MSI to a given address, with a programmed value. This in turn triggers an SPI interrupt. This worked with EDK2 and older versions of u-boot, but in the newer ones the mappNormally MSI vector should be allocated by ICUs parent and set during is no longer done therenterrupt allocation. With this patch irq number is allocated in GICP/SEI and passed down to ICU which does the mappingInstead of doing that we relied on the ICU being pre-configured in firmware. This allows us to worked with EDK2 and older versions of u-boot on armada 7k/8k board, but in the newer ones that run modern ubootis no longer the case. For SATA interrupts we needExtend ICU msi-parents - GICP and SEI to apply a WA previously done in firmwaresupport MSI interface and use it during interrupt allocation. We have two SATA ports connectedThis allows us to one controller. Each ports gets its own interrupt, but only one of them isboot on armada 7k/8k SoCs that run modern uboot. described in dts, also ahci_generic driver expects only For SATA interrupts we need to apply a WA previously done irq per controllern firmware. Fix it by mapping both CP110 interrupts when one of them is allocatedWe have two SATA ports connected to one controller. This way the same irq is triggerEach ports gets its own interrupt, but only one of them is described in GICP when either port fires an interruptdts, also ahci_generic driver expects only one irq too. In the case of SEI we have two types of interrupts - ones that are directly connected to AP806 and others that are routed through CP110. The former require 1:1 mappingFix it by mapping both interrupts to the same MSI when one of them is allocated, the latter are handled in the same way as interrupts in GICPwhich allows us to use both SATA ports.