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Fix the offset for the CPU0 MPIC registers.

Description

Fix the offset for the CPU0 MPIC registers.

Please note that only a subset of CPU0 registers are exported. CPU1
registers are not touched.

Obtained from: ARMADA38X Functional Specifications
Sponsored by: Rubicon Communications, LLC (Netgate)

Details

Committed
loosMay 17 2017, 10:05 PM
Parents
rS318427: Add tri-mode support (SAS/SATA/PCIe).
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