Map BAR 4/5, because NVMe spec says devices may place the MSI-X table
behind BAR 4/5, rather than in BAR 0/1 with the control/doorbell registers.
Sponsored by: Intel
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Details
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jimharris Authored on Dec 18 2012, 11:27 PM - Parents
- rG90576f541b81: Add sysctls for changing GPIO pins function
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