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sys/arm64/include/armreg.h
| Show First 20 Lines • Show All 765 Lines • ▼ Show 20 Lines | |||||
| #define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) | #define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) | ||||
| #define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) | #define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) | ||||
| #define ID_AA64PFR1_RAS_frac_SHIFT 12 | #define ID_AA64PFR1_RAS_frac_SHIFT 12 | ||||
| #define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) | #define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) | ||||
| #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) | #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) | ||||
| #define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) | #define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) | ||||
| #define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) | #define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) | ||||
| /* ID_ISAR5_EL1 */ | |||||
| #define ID_ISAR5_EL1 MRS_REG(3, 0, 0, 2, 5) | |||||
andrew: We don't normally add `_EL1` on these definitions | |||||
| #define ID_ISAR5_SEVL_SHIFT 0 | |||||
| #define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT) | |||||
| #define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) | |||||
| #define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT) | |||||
| #define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT) | |||||
| #define ID_ISAR5_AES_SHIFT 4 | |||||
| #define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT) | |||||
| #define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) | |||||
| #define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT) | |||||
| #define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT) | |||||
| #define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT) | |||||
| #define ID_ISAR5_SHA1_SHIFT 8 | |||||
| #define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT) | |||||
| #define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) | |||||
| #define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT) | |||||
| #define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT) | |||||
| #define ID_ISAR5_SHA2_SHIFT 12 | |||||
| #define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT) | |||||
| #define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) | |||||
| #define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT) | |||||
| #define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT) | |||||
| #define ID_ISAR5_CRC32_SHIFT 16 | |||||
| #define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT) | |||||
| #define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) | |||||
| #define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT) | |||||
| #define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT) | |||||
| #define ID_ISAR5_RDM_SHIFT 24 | |||||
| #define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT) | |||||
| #define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) | |||||
| #define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT) | |||||
| #define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT) | |||||
| #define ID_ISAR5_VCMA_SHIFT 28 | |||||
| #define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT) | |||||
| #define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) | |||||
| #define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT) | |||||
| #define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT) | |||||
Not Done Inline ActionsUL(0x01) andrew: `UL(0x01)` | |||||
| /* MAIR_EL1 - Memory Attribute Indirection Register */ | /* MAIR_EL1 - Memory Attribute Indirection Register */ | ||||
| #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) | #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) | ||||
| #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) | #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) | ||||
Not Done Inline ActionsI've been following capitalisation from the documentation to help auto generate these registers so these would be ID_PFR0_State... andrew: I've been following capitalisation from the documentation to help auto generate these registers… | |||||
| #define MAIR_DEVICE_nGnRnE 0x00 | #define MAIR_DEVICE_nGnRnE 0x00 | ||||
| #define MAIR_DEVICE_nGnRE 0x04 | #define MAIR_DEVICE_nGnRE 0x04 | ||||
| #define MAIR_NORMAL_NC 0x44 | #define MAIR_NORMAL_NC 0x44 | ||||
| #define MAIR_NORMAL_WT 0xbb | #define MAIR_NORMAL_WT 0xbb | ||||
| #define MAIR_NORMAL_WB 0xff | #define MAIR_NORMAL_WB 0xff | ||||
| /* MVFR0_EL1 */ | |||||
| #define MVFR0_EL1 MRS_REG(3, 0, 0, 3, 0) | |||||
| #define MVFR0_SIMDReg_SHIFT 0 | |||||
| #define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT) | |||||
| #define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) | |||||
| #define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT) | |||||
| #define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT) | |||||
| #define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT) | |||||
| #define MVFR0_FPSP_SHIFT 4 | |||||
| #define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT) | |||||
| #define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) | |||||
| #define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT) | |||||
| #define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT) | |||||
| #define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT) | |||||
| #define MVFR0_FPDP_SHIFT 8 | |||||
| #define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT) | |||||
| #define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) | |||||
| #define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT) | |||||
| #define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT) | |||||
| #define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT) | |||||
Not Done Inline ActionsMaybe call this ID_PFR0_EL1_CSV2_HWCTX as later revisions of the architecture add a variant that branch targets trained on both different hardware contexts and different addresses can control speculative execution on different hardware contexts and addresses respectively. andrew: Maybe call this `ID_PFR0_EL1_CSV2_HWCTX` as later revisions of the architecture add a variant… | |||||
| #define MVFR0_FPTrap_SHIFT 12 | |||||
| #define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT) | |||||
| #define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) | |||||
| #define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT) | |||||
| #define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT) | |||||
| #define MVFR0_FPDivide_SHIFT 16 | |||||
| #define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT) | |||||
| #define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) | |||||
| #define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT) | |||||
| #define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT) | |||||
| #define MVFR0_FPSqrt_SHIFT 20 | |||||
| #define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT) | |||||
| #define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) | |||||
| #define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT) | |||||
| #define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT) | |||||
| #define MVFR0_FPShVec_SHIFT 24 | |||||
Not Done Inline ActionsFPShVec andrew: `FPShVec` | |||||
| #define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT) | |||||
Not Done Inline ActionsUL(0x2) andrew: `UL(0x2)` | |||||
| #define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) | |||||
| #define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT) | |||||
| #define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT) | |||||
| #define MVFR0_FPRound_SHIFT 28 | |||||
| #define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT) | |||||
| #define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) | |||||
| #define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT) | |||||
| #define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT) | |||||
| /* MVFR1_EL1 */ | |||||
| #define MVFR1_EL1 MRS_REG(3, 0, 0, 3, 1) | |||||
| #define MVFR1_FPFtZ_SHIFT 0 | |||||
| #define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT) | |||||
| #define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) | |||||
| #define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT) | |||||
| #define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT) | |||||
| #define MVFR1_FPDNaN_SHIFT 4 | |||||
| #define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT) | |||||
| #define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) | |||||
| #define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT) | |||||
| #define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT) | |||||
| #define MVFR1_SIMDLS_SHIFT 8 | |||||
| #define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT) | |||||
| #define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) | |||||
| #define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT) | |||||
| #define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT) | |||||
| #define MVFR1_SIMDInt_SHIFT 12 | |||||
| #define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT) | |||||
| #define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) | |||||
| #define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT) | |||||
| #define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT) | |||||
| #define MVFR1_SIMDSP_SHIFT 16 | |||||
| #define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT) | |||||
| #define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) | |||||
| #define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT) | |||||
| #define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT) | |||||
| #define MVFR1_SIMDHP_SHIFT 20 | |||||
| #define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT) | |||||
| #define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) | |||||
| #define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT) | |||||
| #define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT) | |||||
| #define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT) | |||||
Not Done Inline ActionsMaybe MVFR1_SIMDHP_CONV (or _CONV_SP) and MVFR1_SIMDHP_ARITH so it's obvious the former only allows for conversion, while the latter adds arithmetic operations. andrew: Maybe `MVFR1_SIMDHP_CONV` (or `_CONV_SP`) and `MVFR1_SIMDHP_ARITH` so it's obvious the former… | |||||
| #define MVFR1_FPHP_SHIFT 24 | |||||
| #define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT) | |||||
| #define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) | |||||
| #define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT) | |||||
| #define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT) | |||||
| #define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT) | |||||
Not Done Inline ActionsMaybe MVFR1_FPHP_CONV_SP and MVFR1_FPHP_CONV_DP and add MVFR1_FPHP_CONV_ARITH (UL(0x3)...) to indicate support for half-precision arithmetic operations. andrew: Maybe `MVFR1_FPHP_CONV_SP` and `MVFR1_FPHP_CONV_DP` and add `MVFR1_FPHP_CONV_ARITH (UL(0x3)... | |||||
| #define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT) | |||||
| #define MVFR1_SIMDFMAC_SHIFT 28 | |||||
| #define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT) | |||||
| #define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) | |||||
| #define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT) | |||||
| #define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT) | |||||
| /* PAR_EL1 - Physical Address Register */ | /* PAR_EL1 - Physical Address Register */ | ||||
| #define PAR_F_SHIFT 0 | #define PAR_F_SHIFT 0 | ||||
| #define PAR_F (0x1 << PAR_F_SHIFT) | #define PAR_F (0x1 << PAR_F_SHIFT) | ||||
| #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) | #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) | ||||
| /* When PAR_F == 0 (success) */ | /* When PAR_F == 0 (success) */ | ||||
| #define PAR_LOW_MASK 0xfff | #define PAR_LOW_MASK 0xfff | ||||
| #define PAR_SH_SHIFT 7 | #define PAR_SH_SHIFT 7 | ||||
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We don't normally add _EL1 on these definitions