Changeset View
Changeset View
Standalone View
Standalone View
sys/powerpc/aim/trap_subr64.S
| Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines | |||||
| /* | /* | ||||
| * Restore SRs for a pmap | * Restore SRs for a pmap | ||||
| * | * | ||||
| * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache | * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache | ||||
| */ | */ | ||||
| /* | /* | ||||
| * User SRs are loaded through a pointer to the current pmap. | * User SRs are loaded through a pointer to the current pmap. | ||||
| * PCPU already in %r3 | |||||
| */ | */ | ||||
| restore_usersrs: | restore_usersrs: | ||||
| GET_CPUINFO(%r28) | ld %r28,PC_USERSLB(%r3) | ||||
| ld %r28,PC_USERSLB(%r28) | |||||
| cmpdi %r28, 0 /* If user SLB pointer NULL, exit */ | cmpdi %r28, 0 /* If user SLB pointer NULL, exit */ | ||||
| beqlr | beqlr | ||||
| li %r29, 0 /* Set the counter to zero */ | li %r29, 0 /* Set the counter to zero */ | ||||
| slbia | slbia | ||||
| slbmfee %r31,%r29 | slbmfee %r31,%r29 | ||||
| clrrdi %r31,%r31,28 | clrrdi %r31,%r31,28 | ||||
| slbie %r31 | slbie %r31 | ||||
| 1: ld %r31, 0(%r28) /* Load SLB entry pointer */ | 1: ld %r31, 0(%r28) /* Load SLB entry pointer */ | ||||
| cmpdi %r31, 0 /* If NULL, stop */ | cmpdi %r31, 0 /* If NULL, stop */ | ||||
| beqlr | beqlr | ||||
| ld %r30, 0(%r31) /* Load SLBV */ | ld %r30, 0(%r31) /* Load SLBV */ | ||||
| ld %r31, 8(%r31) /* Load SLBE */ | ld %r31, 8(%r31) /* Load SLBE */ | ||||
| or %r31, %r31, %r29 /* Set SLBE slot */ | or %r31, %r31, %r29 /* Set SLBE slot */ | ||||
| slbmte %r30, %r31 /* Install SLB entry */ | slbmte %r30, %r31 /* Install SLB entry */ | ||||
| addi %r28, %r28, 8 /* Advance pointer */ | addi %r28, %r28, 8 /* Advance pointer */ | ||||
| addi %r29, %r29, 1 | addi %r29, %r29, 1 | ||||
| b 1b /* Repeat */ | b 1b /* Repeat */ | ||||
| /* | /* | ||||
| * Kernel SRs are loaded directly from the PCPU fields | * Kernel SRs are loaded directly from the PCPU fields | ||||
| * PCPU in %r1 | |||||
| */ | */ | ||||
| restore_kernsrs: | restore_kernsrs: | ||||
| GET_CPUINFO(%r28) | lwz %r29, PC_FLAGS(%r1) | ||||
| lwz %r29, PC_FLAGS(%r28) | |||||
| mtcr %r29 | mtcr %r29 | ||||
| btlr 0 | btlr 0 | ||||
| addi %r28,%r28,PC_KERNSLB | addi %r28,%r1,PC_KERNSLB | ||||
| ld %r29,16(%r28) /* One past USER_SLB_SLOT */ | ld %r29,16(%r28) /* One past USER_SLB_SLOT */ | ||||
| cmpdi %r29,0 | cmpdi %r29,0 | ||||
| beqlr /* If first kernel entry is invalid, | beqlr /* If first kernel entry is invalid, | ||||
| * SLBs not in use, so exit early */ | * SLBs not in use, so exit early */ | ||||
| /* Otherwise, set up SLBs */ | /* Otherwise, set up SLBs */ | ||||
| li %r29, 0 /* Set the counter to zero */ | li %r29, 0 /* Set the counter to zero */ | ||||
| ▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines | |||||
| /* Decide whether we return to user mode: */ \ | /* Decide whether we return to user mode: */ \ | ||||
| GET_CPUINFO(%r3); \ | GET_CPUINFO(%r3); \ | ||||
| ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \ | ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \ | ||||
| mtcr %r3; \ | mtcr %r3; \ | ||||
| bf 17,1f; /* branch if PSL_PR is false */ \ | bf 17,1f; /* branch if PSL_PR is false */ \ | ||||
| /* Restore user SRs */ \ | /* Restore user SRs */ \ | ||||
| GET_CPUINFO(%r3); \ | GET_CPUINFO(%r3); \ | ||||
| std %r27,(savearea+CPUSAVE_R27)(%r3); \ | std %r27,(savearea+CPUSAVE_R27)(%r3); \ | ||||
| lwz %r27,PC_FLAGS(%r3); \ | |||||
| mtcr %r27; \ | |||||
| bt 0, 0f; /* Check to skip restoring SRs. */ \ | |||||
| std %r28,(savearea+CPUSAVE_R28)(%r3); \ | std %r28,(savearea+CPUSAVE_R28)(%r3); \ | ||||
| std %r29,(savearea+CPUSAVE_R29)(%r3); \ | std %r29,(savearea+CPUSAVE_R29)(%r3); \ | ||||
| std %r30,(savearea+CPUSAVE_R30)(%r3); \ | std %r30,(savearea+CPUSAVE_R30)(%r3); \ | ||||
| std %r31,(savearea+CPUSAVE_R31)(%r3); \ | std %r31,(savearea+CPUSAVE_R31)(%r3); \ | ||||
| lwz %r28,PC_FLAGS(%r3); \ | |||||
| mtcr %r28; \ | |||||
| bt 0, 0f; /* Check to skip restoring SRs. */ \ | |||||
| mflr %r27; /* preserve LR */ \ | mflr %r27; /* preserve LR */ \ | ||||
| bl restore_usersrs; /* uses r28-r31 */ \ | bl restore_usersrs; /* uses r28-r31 */ \ | ||||
| mtlr %r27; \ | mtlr %r27; \ | ||||
| 0: \ | |||||
| ld %r31,(savearea+CPUSAVE_R31)(%r3); \ | ld %r31,(savearea+CPUSAVE_R31)(%r3); \ | ||||
| ld %r30,(savearea+CPUSAVE_R30)(%r3); \ | ld %r30,(savearea+CPUSAVE_R30)(%r3); \ | ||||
| ld %r29,(savearea+CPUSAVE_R29)(%r3); \ | ld %r29,(savearea+CPUSAVE_R29)(%r3); \ | ||||
| ld %r28,(savearea+CPUSAVE_R28)(%r3); \ | ld %r28,(savearea+CPUSAVE_R28)(%r3); \ | ||||
| 0: \ | |||||
| ld %r27,(savearea+CPUSAVE_R27)(%r3); \ | ld %r27,(savearea+CPUSAVE_R27)(%r3); \ | ||||
| 1: mfsprg2 %r3; /* restore cr */ \ | 1: mfsprg2 %r3; /* restore cr */ \ | ||||
| mtcr %r3; \ | mtcr %r3; \ | ||||
| GET_CPUINFO(%r3); \ | GET_CPUINFO(%r3); \ | ||||
| ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \ | ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \ | ||||
| mtsrr0 %r3; \ | mtsrr0 %r3; \ | ||||
| GET_CPUINFO(%r3); \ | GET_CPUINFO(%r3); \ | ||||
| ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \ | ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \ | ||||
| ▲ Show 20 Lines • Show All 478 Lines • ▼ Show 20 Lines | |||||
| realtrap: | realtrap: | ||||
| /* Test whether we already had PR set */ | /* Test whether we already had PR set */ | ||||
| mfsrr1 %r1 | mfsrr1 %r1 | ||||
| mtcr %r1 | mtcr %r1 | ||||
| mfsprg1 %r1 /* restore SP (might have been | mfsprg1 %r1 /* restore SP (might have been | ||||
| overwritten) */ | overwritten) */ | ||||
| bf 17,k_trap /* branch if PSL_PR is false */ | bf 17,k_trap /* branch if PSL_PR is false */ | ||||
| GET_CPUINFO(%r1) | GET_CPUINFO(%r1) | ||||
| ld %r1,PC_CURPCB(%r1) | |||||
| mr %r27,%r28 /* Save LR, r29 */ | mr %r27,%r28 /* Save LR, r29 */ | ||||
| mtsprg2 %r29 | mtsprg2 %r29 | ||||
| bl restore_kernsrs /* enable kernel mapping */ | bl restore_kernsrs /* enable kernel mapping */ | ||||
| mfsprg2 %r29 | mfsprg2 %r29 | ||||
| mr %r28,%r27 | mr %r28,%r27 | ||||
| ld %r1,PC_CURPCB(%r1) | |||||
| b s_trap | b s_trap | ||||
| /* | /* | ||||
| * generictrap does some standard setup for trap handling to minimize | * generictrap does some standard setup for trap handling to minimize | ||||
| * the code that need be installed in the actual vectors. It expects | * the code that need be installed in the actual vectors. It expects | ||||
| * the following conditions. | * the following conditions. | ||||
| * | * | ||||
| * R1 - Trap vector = LR & (0xff00 | R1) | * R1 - Trap vector = LR & (0xff00 | R1) | ||||
| Show All 39 Lines | generictrap: | ||||
| /* Test whether we already had PR set */ | /* Test whether we already had PR set */ | ||||
| mfsrr1 %r31 | mfsrr1 %r31 | ||||
| mtcr %r31 | mtcr %r31 | ||||
| s_trap: | s_trap: | ||||
| bf 17,k_trap /* branch if PSL_PR is false */ | bf 17,k_trap /* branch if PSL_PR is false */ | ||||
| GET_CPUINFO(%r1) | GET_CPUINFO(%r1) | ||||
| u_trap: | u_trap: | ||||
| ld %r1,PC_CURPCB(%r1) | |||||
| mr %r27,%r28 /* Save LR, r29 */ | mr %r27,%r28 /* Save LR, r29 */ | ||||
| mtsprg2 %r29 | mtsprg2 %r29 | ||||
| bl restore_kernsrs /* enable kernel mapping */ | bl restore_kernsrs /* enable kernel mapping */ | ||||
| mfsprg2 %r29 | mfsprg2 %r29 | ||||
| mr %r28,%r27 | mr %r28,%r27 | ||||
| ld %r1,PC_CURPCB(%r1) | |||||
| /* | /* | ||||
| * Now the common trap catching code. | * Now the common trap catching code. | ||||
| */ | */ | ||||
| k_trap: | k_trap: | ||||
| FRAME_SETUP(PC_TEMPSAVE) | FRAME_SETUP(PC_TEMPSAVE) | ||||
| /* Call C interrupt dispatcher: */ | /* Call C interrupt dispatcher: */ | ||||
| trapagain: | trapagain: | ||||
| ▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines | |||||