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Differential D30033 Diff 88454 sys/arm64/arm64/gicv3_its.c

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sys/arm64/arm64/gicv3_its.c

Show First 20 Lines • Show All 1,191 Lines • ▼ Show 20 Lines its_dev->itt = (vm_offset_t)contigmalloc_domainset(its_dev->itt_size,
M_GICV3_ITS, sc->sc_ds, M_NOWAIT | M_ZERO, 0, M_GICV3_ITS, sc->sc_ds, M_NOWAIT | M_ZERO, 0,
LPI_INT_TRANS_TAB_MAX_ADDR, LPI_INT_TRANS_TAB_ALIGN, 0); LPI_INT_TRANS_TAB_MAX_ADDR, LPI_INT_TRANS_TAB_ALIGN, 0);
if (its_dev->itt == 0) { if (its_dev->itt == 0) {
vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base, nvecs); vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base, nvecs);
free(its_dev, M_GICV3_ITS); free(its_dev, M_GICV3_ITS);
return (NULL); return (NULL);
} }
/* Make sure device sees zeroed ITT. */
if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0)
cpu_dcache_wb_range(its_dev->itt, its_dev->itt_size);
andrewUnsubmitted
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I think we want a dsb(ishst); in the else case to ensure any previous writes to itt are complete. We might get it via the spinlock below, but shouldn't rely on it.

andrew: I think we want a `dsb(ishst);` in the else case to ensure any previous writes to `itt` are…
kdAuthorUnsubmitted
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I though about it and I don't think it is necessary here.
Before itt is committed to the ITS its_cmd_sync will be called, which does dsb(ishst); for cache-coherent devices.

kd: I though about it and I don't think it is necessary here. Before itt is committed to the ITS…
mtx_lock_spin(&sc->sc_its_dev_lock); mtx_lock_spin(&sc->sc_its_dev_lock);
TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry); TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
mtx_unlock_spin(&sc->sc_its_dev_lock); mtx_unlock_spin(&sc->sc_its_dev_lock);
/* Map device to its ITT */ /* Map device to its ITT */
its_cmd_mapd(dev, its_dev, 1); its_cmd_mapd(dev, its_dev, 1);
return (its_dev); return (its_dev);
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