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head/sys/riscv/riscv/exception.S
| Show All 34 Lines | |||||
| #include <machine/asm.h> | #include <machine/asm.h> | ||||
| __FBSDID("$FreeBSD$"); | __FBSDID("$FreeBSD$"); | ||||
| #include "assym.inc" | #include "assym.inc" | ||||
| #include <machine/trap.h> | #include <machine/trap.h> | ||||
| #include <machine/riscvreg.h> | #include <machine/riscvreg.h> | ||||
| .macro save_registers el | .macro save_registers mode | ||||
| addi sp, sp, -(TF_SIZE) | addi sp, sp, -(TF_SIZE) | ||||
| sd ra, (TF_RA)(sp) | sd ra, (TF_RA)(sp) | ||||
| .if \el == 0 /* We came from userspace. */ | .if \mode == 0 /* We came from userspace. */ | ||||
| sd gp, (TF_GP)(sp) | sd gp, (TF_GP)(sp) | ||||
| .option push | .option push | ||||
| .option norelax | .option norelax | ||||
| /* Load the kernel's global pointer */ | /* Load the kernel's global pointer */ | ||||
| la gp, __global_pointer$ | la gp, __global_pointer$ | ||||
| .option pop | .option pop | ||||
| /* Load our pcpu */ | /* Load our pcpu */ | ||||
| Show All 26 Lines | .endif | ||||
| sd a1, (TF_A + 1 * 8)(sp) | sd a1, (TF_A + 1 * 8)(sp) | ||||
| sd a2, (TF_A + 2 * 8)(sp) | sd a2, (TF_A + 2 * 8)(sp) | ||||
| sd a3, (TF_A + 3 * 8)(sp) | sd a3, (TF_A + 3 * 8)(sp) | ||||
| sd a4, (TF_A + 4 * 8)(sp) | sd a4, (TF_A + 4 * 8)(sp) | ||||
| sd a5, (TF_A + 5 * 8)(sp) | sd a5, (TF_A + 5 * 8)(sp) | ||||
| sd a6, (TF_A + 6 * 8)(sp) | sd a6, (TF_A + 6 * 8)(sp) | ||||
| sd a7, (TF_A + 7 * 8)(sp) | sd a7, (TF_A + 7 * 8)(sp) | ||||
| .if \el == 1 | .if \mode == 1 | ||||
| /* Store kernel sp */ | /* Store kernel sp */ | ||||
| li t1, TF_SIZE | li t1, TF_SIZE | ||||
| add t0, sp, t1 | add t0, sp, t1 | ||||
| sd t0, (TF_SP)(sp) | sd t0, (TF_SP)(sp) | ||||
| .else | .else | ||||
| /* Store user sp */ | /* Store user sp */ | ||||
| csrr t0, sscratch | csrr t0, sscratch | ||||
| sd t0, (TF_SP)(sp) | sd t0, (TF_SP)(sp) | ||||
| .endif | .endif | ||||
| li t0, 0 | li t0, 0 | ||||
| csrw sscratch, t0 | csrw sscratch, t0 | ||||
| csrr t0, sepc | csrr t0, sepc | ||||
| sd t0, (TF_SEPC)(sp) | sd t0, (TF_SEPC)(sp) | ||||
| csrr t0, sstatus | csrr t0, sstatus | ||||
| sd t0, (TF_SSTATUS)(sp) | sd t0, (TF_SSTATUS)(sp) | ||||
| csrr t0, stval | csrr t0, stval | ||||
| sd t0, (TF_STVAL)(sp) | sd t0, (TF_STVAL)(sp) | ||||
| csrr t0, scause | csrr t0, scause | ||||
| sd t0, (TF_SCAUSE)(sp) | sd t0, (TF_SCAUSE)(sp) | ||||
| .endm | .endm | ||||
| .macro load_registers el | .macro load_registers mode | ||||
| ld t0, (TF_SSTATUS)(sp) | ld t0, (TF_SSTATUS)(sp) | ||||
| .if \el == 0 | .if \mode == 0 | ||||
| /* Ensure user interrupts will be enabled on eret */ | /* Ensure user interrupts will be enabled on eret */ | ||||
| li t1, SSTATUS_SPIE | li t1, SSTATUS_SPIE | ||||
| or t0, t0, t1 | or t0, t0, t1 | ||||
| .else | .else | ||||
| /* | /* | ||||
| * Disable interrupts for supervisor mode exceptions. | * Disable interrupts for supervisor mode exceptions. | ||||
| * For user mode exceptions we have already done this | * For user mode exceptions we have already done this | ||||
| * in do_ast. | * in do_ast. | ||||
| */ | */ | ||||
| li t1, ~SSTATUS_SIE | li t1, ~SSTATUS_SIE | ||||
| and t0, t0, t1 | and t0, t0, t1 | ||||
| .endif | .endif | ||||
| csrw sstatus, t0 | csrw sstatus, t0 | ||||
| ld t0, (TF_SEPC)(sp) | ld t0, (TF_SEPC)(sp) | ||||
| csrw sepc, t0 | csrw sepc, t0 | ||||
| .if \el == 0 | .if \mode == 0 | ||||
| /* We go to userspace. Load user sp */ | /* We go to userspace. Load user sp */ | ||||
| ld t0, (TF_SP)(sp) | ld t0, (TF_SP)(sp) | ||||
| csrw sscratch, t0 | csrw sscratch, t0 | ||||
| /* Store our pcpu */ | /* Store our pcpu */ | ||||
| sd tp, (TF_SIZE)(sp) | sd tp, (TF_SIZE)(sp) | ||||
| ld tp, (TF_TP)(sp) | ld tp, (TF_TP)(sp) | ||||
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