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sys/x86/include/specialreg.h
| Show First 20 Lines • Show All 1,120 Lines • ▼ Show 20 Lines | |||||
| #define MSR_IORRMASK0 0xc0010017 | #define MSR_IORRMASK0 0xc0010017 | ||||
| #define MSR_IORRBASE1 0xc0010018 | #define MSR_IORRBASE1 0xc0010018 | ||||
| #define MSR_IORRMASK1 0xc0010019 | #define MSR_IORRMASK1 0xc0010019 | ||||
| #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ | #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ | ||||
| #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ | #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ | ||||
| #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ | #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ | ||||
| #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ | #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ | ||||
| #define MSR_MC0_CTL_MASK 0xc0010044 | #define MSR_MC0_CTL_MASK 0xc0010044 | ||||
| #define MSR_AMDK8_IPM 0xc0010055 | |||||
| #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ | #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ | ||||
| #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ | #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ | ||||
| #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ | #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ | ||||
| #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ | #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ | ||||
| #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ | #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ | ||||
| #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ | #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ | ||||
| #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ | #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ | ||||
| #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ | #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ | ||||
| #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */ | #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */ | ||||
| #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ | #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ | ||||
| #define MSR_LS_CFG 0xc0011020 | #define MSR_LS_CFG 0xc0011020 | ||||
| #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ | #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ | ||||
| #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ | #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ | ||||
| /* MSR_VM_CR related */ | /* MSR_VM_CR related */ | ||||
| #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ | #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ | ||||
| #define AMDK8_SMIONCMPHALT (1ULL << 27) | |||||
| #define AMDK8_C1EONCMPHALT (1ULL << 28) | |||||
| /* VIA ACE crypto featureset: for via_feature_rng */ | /* VIA ACE crypto featureset: for via_feature_rng */ | ||||
| #define VIA_HAS_RNG 1 /* cpu has RNG */ | #define VIA_HAS_RNG 1 /* cpu has RNG */ | ||||
| /* VIA ACE crypto featureset: for via_feature_xcrypt */ | /* VIA ACE crypto featureset: for via_feature_xcrypt */ | ||||
| #define VIA_HAS_AES 1 /* cpu has AES */ | #define VIA_HAS_AES 1 /* cpu has AES */ | ||||
| #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ | #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ | ||||
| #define VIA_HAS_MM 4 /* cpu has RSA instructions */ | #define VIA_HAS_MM 4 /* cpu has RSA instructions */ | ||||
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