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Differential D26029 Diff 75695 sys/arm64/arm64/identcpu.c

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sys/arm64/arm64/identcpu.c

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/* ID_AA64DFR1 */ /* ID_AA64DFR1 */
static struct mrs_field id_aa64dfr1_fields[] = { static struct mrs_field id_aa64dfr1_fields[] = {
MRS_FIELD_END, MRS_FIELD_END,
}; };
/* ID_AA64ISAR0_EL1 */ /* ID_AA64ISAR0_EL1 */
static struct mrs_field_value id_aa64isar0_rndr[] = {
MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""),
MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar0_tlb[] = {
MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""),
MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_IMPL, "TLBI"),
markjUnsubmitted
Done
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"TLBIOS" and "TLBIOSR" perhaps?

markj: "TLBIOS" and "TLBIOSR" perhaps?
andrewUnsubmitted
Done
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We should give the macros better names, and report them differently so we can tell which we have from dmesg.

andrew: We should give the macros better names, and report them differently so we can tell which we…
MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_IMPL2, "TLBI"),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar0_ts[] = {
MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""),
MRS_FIELD_VALUE(ID_AA64ISAR0_TS_FLAGM, "CondM"),
MRS_FIELD_VALUE(ID_AA64ISAR0_TS_FLAGM2, "CondM-8.5"),
andrewUnsubmitted
Done
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Can you give the macros better names, e.g. _TS_CondM_8_4 and _TS_CondM_8_5

andrew: Can you give the macros better names, e.g. `_TS_CondM_8_4` and `_TS_CondM_8_5`
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar0_fhm[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar0_dp[] = { static struct mrs_field_value id_aa64isar0_dp[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field_value id_aa64isar0_sm4[] = { static struct mrs_field_value id_aa64isar0_sm4[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM4, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM4, NONE, IMPL),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
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static struct mrs_field_value id_aa64isar0_aes[] = { static struct mrs_field_value id_aa64isar0_aes[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE),
MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"), MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field id_aa64isar0_fields[] = { static struct mrs_field id_aa64isar0_fields[] = {
MRS_FIELD(ID_AA64ISAR0, RNDR, false, MRS_LOWER, id_aa64isar0_rndr),
MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_LOWER, id_aa64isar0_tlb),
MRS_FIELD(ID_AA64ISAR0, TS, false, MRS_LOWER, id_aa64isar0_ts),
MRS_FIELD(ID_AA64ISAR0, FHM, false, MRS_LOWER, id_aa64isar0_fhm),
MRS_FIELD(ID_AA64ISAR0, DP, false, MRS_LOWER, id_aa64isar0_dp), MRS_FIELD(ID_AA64ISAR0, DP, false, MRS_LOWER, id_aa64isar0_dp),
MRS_FIELD(ID_AA64ISAR0, SM4, false, MRS_LOWER, id_aa64isar0_sm4), MRS_FIELD(ID_AA64ISAR0, SM4, false, MRS_LOWER, id_aa64isar0_sm4),
MRS_FIELD(ID_AA64ISAR0, SM3, false, MRS_LOWER, id_aa64isar0_sm3), MRS_FIELD(ID_AA64ISAR0, SM3, false, MRS_LOWER, id_aa64isar0_sm3),
MRS_FIELD(ID_AA64ISAR0, SHA3, false, MRS_LOWER, id_aa64isar0_sha3), MRS_FIELD(ID_AA64ISAR0, SHA3, false, MRS_LOWER, id_aa64isar0_sha3),
MRS_FIELD(ID_AA64ISAR0, RDM, false, MRS_LOWER, id_aa64isar0_rdm), MRS_FIELD(ID_AA64ISAR0, RDM, false, MRS_LOWER, id_aa64isar0_rdm),
MRS_FIELD(ID_AA64ISAR0, Atomic, false, MRS_LOWER, id_aa64isar0_atomic), MRS_FIELD(ID_AA64ISAR0, Atomic, false, MRS_LOWER, id_aa64isar0_atomic),
MRS_FIELD(ID_AA64ISAR0, CRC32, false, MRS_LOWER, id_aa64isar0_crc32), MRS_FIELD(ID_AA64ISAR0, CRC32, false, MRS_LOWER, id_aa64isar0_crc32),
MRS_FIELD(ID_AA64ISAR0, SHA2, false, MRS_LOWER, id_aa64isar0_sha2), MRS_FIELD(ID_AA64ISAR0, SHA2, false, MRS_LOWER, id_aa64isar0_sha2),
MRS_FIELD(ID_AA64ISAR0, SHA1, false, MRS_LOWER, id_aa64isar0_sha1), MRS_FIELD(ID_AA64ISAR0, SHA1, false, MRS_LOWER, id_aa64isar0_sha1),
MRS_FIELD(ID_AA64ISAR0, AES, false, MRS_LOWER, id_aa64isar0_aes), MRS_FIELD(ID_AA64ISAR0, AES, false, MRS_LOWER, id_aa64isar0_aes),
MRS_FIELD_END, MRS_FIELD_END,
}; };
/* ID_AA64ISAR1_EL1 */ /* ID_AA64ISAR1_EL1 */
static struct mrs_field_value id_aa64isar1_i8mm[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_dgh[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_bf16[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_specres[] = {
MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""),
MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_IMPL, "PredInv"),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_sb[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_frintts[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_gpi[] = { static struct mrs_field_value id_aa64isar1_gpi[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field_value id_aa64isar1_gpa[] = { static struct mrs_field_value id_aa64isar1_gpa[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field_value id_aa64isar1_lrcpc[] = { static struct mrs_field_value id_aa64isar1_lrcpc[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LRCPC, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LRCPC, NONE, IMPL),
MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_ILRCPC, "LRCPC-8.4"),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field_value id_aa64isar1_fcma[] = { static struct mrs_field_value id_aa64isar1_fcma[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FCMA, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FCMA, NONE, IMPL),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field_value id_aa64isar1_jscvt[] = { static struct mrs_field_value id_aa64isar1_jscvt[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, JSCVT, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, JSCVT, NONE, IMPL),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field_value id_aa64isar1_api[] = { static struct mrs_field_value id_aa64isar1_api[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, API, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, API, NONE, IMPL),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field_value id_aa64isar1_apa[] = { static struct mrs_field_value id_aa64isar1_apa[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL), MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, APA, NONE, IMPL),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field_value id_aa64isar1_dpb[] = { static struct mrs_field_value id_aa64isar1_dpb[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DPB, NONE, IMPL), MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""),
MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"),
MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"),
MRS_FIELD_VALUE_END, MRS_FIELD_VALUE_END,
}; };
static struct mrs_field id_aa64isar1_fields[] = { static struct mrs_field id_aa64isar1_fields[] = {
MRS_FIELD(ID_AA64ISAR1, I8MM, false, MRS_EXACT, id_aa64isar1_i8mm),
mhorneAuthorUnsubmitted
Done
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What is the distinction between MRS_EXACT and MRS_LOWER? I looked but had a hard time understanding the purpose.

mhorne: What is the distinction between MRS_EXACT and MRS_LOWER? I looked but had a hard time…
andrewUnsubmitted
Not Done
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MRS_EXACT is shorthand for MRS_EXACT_VAL(0), i.e. always set the field to 0. MRS_LOWER will perform a comparison between the current and new field values and use the lower (signed or unsigned) of the two.

andrew: `MRS_EXACT` is shorthand for `MRS_EXACT_VAL(0)`, i.e. always set the field to 0. `MRS_LOWER`…
MRS_FIELD(ID_AA64ISAR1, DGH, false, MRS_EXACT, id_aa64isar1_dgh),
MRS_FIELD(ID_AA64ISAR1, BF16, false, MRS_EXACT, id_aa64isar1_bf16),
MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_EXACT,
id_aa64isar1_specres),
MRS_FIELD(ID_AA64ISAR1, SB, false, MRS_EXACT, id_aa64isar1_sb),
MRS_FIELD(ID_AA64ISAR1, FRINTTS, false, MRS_EXACT,
id_aa64isar1_frintts),
MRS_FIELD(ID_AA64ISAR1, GPI, false, MRS_EXACT, id_aa64isar1_gpi), MRS_FIELD(ID_AA64ISAR1, GPI, false, MRS_EXACT, id_aa64isar1_gpi),
MRS_FIELD(ID_AA64ISAR1, GPA, false, MRS_EXACT, id_aa64isar1_gpa), MRS_FIELD(ID_AA64ISAR1, GPA, false, MRS_EXACT, id_aa64isar1_gpa),
MRS_FIELD(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, id_aa64isar1_lrcpc), MRS_FIELD(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, id_aa64isar1_lrcpc),
MRS_FIELD(ID_AA64ISAR1, FCMA, false, MRS_LOWER, id_aa64isar1_fcma), MRS_FIELD(ID_AA64ISAR1, FCMA, false, MRS_LOWER, id_aa64isar1_fcma),
MRS_FIELD(ID_AA64ISAR1, JSCVT, false, MRS_LOWER, id_aa64isar1_jscvt), MRS_FIELD(ID_AA64ISAR1, JSCVT, false, MRS_LOWER, id_aa64isar1_jscvt),
MRS_FIELD(ID_AA64ISAR1, API, false, MRS_EXACT, id_aa64isar1_api), MRS_FIELD(ID_AA64ISAR1, API, false, MRS_EXACT, id_aa64isar1_api),
MRS_FIELD(ID_AA64ISAR1, APA, false, MRS_EXACT, id_aa64isar1_apa), MRS_FIELD(ID_AA64ISAR1, APA, false, MRS_EXACT, id_aa64isar1_apa),
MRS_FIELD(ID_AA64ISAR1, DPB, false, MRS_LOWER, id_aa64isar1_dpb), MRS_FIELD(ID_AA64ISAR1, DPB, false, MRS_LOWER, id_aa64isar1_dpb),
▲ Show 20 Lines • Show All 679 Lines • ▼ Show 20 Lines if (ID_AA64ISAR1_LRCPC_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_LRCPC_IMPL)
hwcap |= HWCAP_LRCPC; hwcap |= HWCAP_LRCPC;
if (ID_AA64ISAR1_FCMA_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_FCMA_IMPL) if (ID_AA64ISAR1_FCMA_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_FCMA_IMPL)
hwcap |= HWCAP_FCMA; hwcap |= HWCAP_FCMA;
if (ID_AA64ISAR1_JSCVT_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_JSCVT_IMPL) if (ID_AA64ISAR1_JSCVT_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_JSCVT_IMPL)
hwcap |= HWCAP_JSCVT; hwcap |= HWCAP_JSCVT;
if (ID_AA64ISAR1_DPB_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_DPB_IMPL) if (ID_AA64ISAR1_DPB_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_DPB_DCCVAP)
hwcap |= HWCAP_DCPOP; hwcap |= HWCAP_DCPOP;
if (ID_AA64PFR0_SVE_VAL(cpu_desc[cpu].id_aa64pfr0) == ID_AA64PFR0_SVE_IMPL) if (ID_AA64PFR0_SVE_VAL(cpu_desc[cpu].id_aa64pfr0) == ID_AA64PFR0_SVE_IMPL)
hwcap |= HWCAP_SVE; hwcap |= HWCAP_SVE;
switch (ID_AA64PFR0_AdvSIMD_VAL(cpu_desc[cpu].id_aa64pfr0)) { switch (ID_AA64PFR0_AdvSIMD_VAL(cpu_desc[cpu].id_aa64pfr0)) {
case ID_AA64PFR0_AdvSIMD_IMPL: case ID_AA64PFR0_AdvSIMD_IMPL:
hwcap |= HWCAP_ASIMD; hwcap |= HWCAP_ASIMD;
▲ Show 20 Lines • Show All 399 Lines • Show Last 20 Lines