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sys/x86/iommu/intel_dmar.h
| Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines | struct dmar_unit { | ||||
| dmar_irte_t *irt; | dmar_irte_t *irt; | ||||
| u_int irte_cnt; | u_int irte_cnt; | ||||
| vmem_t *irtids; | vmem_t *irtids; | ||||
| /* Delayed freeing of map entries queue processing */ | /* Delayed freeing of map entries queue processing */ | ||||
| struct iommu_map_entries_tailq tlb_flush_entries; | struct iommu_map_entries_tailq tlb_flush_entries; | ||||
| struct task qi_task; | struct task qi_task; | ||||
| struct taskqueue *qi_taskqueue; | struct taskqueue *qi_taskqueue; | ||||
| /* | |||||
| * Bitmap of buses for which context must ignore slot:func, | |||||
| * duplicating the page table pointer into all context table | |||||
| * entries. This is a client-controlled quirk to support some | |||||
| * NTBs. | |||||
| */ | |||||
| uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)]; | |||||
| }; | }; | ||||
| #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->iommu.lock) | #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->iommu.lock) | ||||
| #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->iommu.lock) | #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->iommu.lock) | ||||
| #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->iommu.lock, MA_OWNED) | #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->iommu.lock, MA_OWNED) | ||||
| #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) | #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) | ||||
| #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) | #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) | ||||
| ▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines | |||||
| int dmar_instantiate_rmrr_ctxs(struct iommu_unit *dmar); | int dmar_instantiate_rmrr_ctxs(struct iommu_unit *dmar); | ||||
| void dmar_quirks_post_ident(struct dmar_unit *dmar); | void dmar_quirks_post_ident(struct dmar_unit *dmar); | ||||
| void dmar_quirks_pre_use(struct iommu_unit *dmar); | void dmar_quirks_pre_use(struct iommu_unit *dmar); | ||||
| int dmar_init_irt(struct dmar_unit *unit); | int dmar_init_irt(struct dmar_unit *unit); | ||||
| void dmar_fini_irt(struct dmar_unit *unit); | void dmar_fini_irt(struct dmar_unit *unit); | ||||
| void dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno); | void iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno); | ||||
| bool dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno); | bool iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno); | ||||
| extern iommu_haddr_t dmar_high; | extern iommu_haddr_t dmar_high; | ||||
| extern int haw; | extern int haw; | ||||
| extern int dmar_tbl_pagecnt; | extern int dmar_tbl_pagecnt; | ||||
| extern int dmar_batch_coalesce; | extern int dmar_batch_coalesce; | ||||
| static inline uint32_t | static inline uint32_t | ||||
| dmar_read4(const struct dmar_unit *unit, int reg) | dmar_read4(const struct dmar_unit *unit, int reg) | ||||
| ▲ Show 20 Lines • Show All 156 Lines • Show Last 20 Lines | |||||