Differential D25225 Diff 73347 head/sys/powerpc/booke/machdep_e500.c

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	booke_enable_l2_cache(void)			booke_enable_l2_cache(void)
	{			{
	uint32_t csr;			uint32_t csr;

	/* Enable L2 cache on E500mc */			/* Enable L2 cache on E500mc */
	if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) \|\|			if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) \|\|
	(((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {			(((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
	csr = mfspr(SPR_L2CSR0);			csr = mfspr(SPR_L2CSR0);
	if ((csr & L2CSR0_L2E) == 0) {			/*
				* Don't actually attempt to manipulate the L2 cache if
				* L2CFG0 is zero.
				*
				* Any chip with a working L2 cache will have a nonzero
				* L2CFG0, as it will have a nonzero L2CSIZE field.
				*
				* This fixes waiting forever for cache enable in qemu,
				* which does not implement the L2 cache.
				*/
				if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) {
	l2cache_inval();			l2cache_inval();
	l2cache_enable();			l2cache_enable();
	}			}

	csr = mfspr(SPR_L2CSR0);			csr = mfspr(SPR_L2CSR0);
	if ((boothowto & RB_VERBOSE) != 0 \|\| (csr & L2CSR0_L2E) == 0)			if ((boothowto & RB_VERBOSE) != 0 \|\| (csr & L2CSR0_L2E) == 0)
	printf("L2 cache %sabled\n",			printf("L2 cache %sabled\n",
	(csr & L2CSR0_L2E) ? "en" : "dis");			(csr & L2CSR0_L2E) ? "en" : "dis");
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