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sys/dev/ixl/i40e_type.h
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/* I40E_MASK is a macro used on 32 bit registers */ | /* I40E_MASK is a macro used on 32 bit registers */ | ||||
#define I40E_MASK(mask, shift) (mask << shift) | #define I40E_MASK(mask, shift) (mask << shift) | ||||
#endif | #endif | ||||
#define I40E_MAX_PF 16 | #define I40E_MAX_PF 16 | ||||
#define I40E_MAX_PF_VSI 64 | #define I40E_MAX_PF_VSI 64 | ||||
#define I40E_MAX_PF_QP 128 | #define I40E_MAX_PF_QP 128 | ||||
#define I40E_MAX_VSI_QP 16 | #define I40E_MAX_VSI_QP 16 | ||||
#define I40E_MAX_VF_VSI 3 | #define I40E_MAX_VF_VSI 4 | ||||
#define I40E_MAX_CHAINED_RX_BUFFERS 5 | #define I40E_MAX_CHAINED_RX_BUFFERS 5 | ||||
#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 | #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 | ||||
/* something less than 1 minute */ | /* something less than 1 minute */ | ||||
#define I40E_HEARTBEAT_TIMEOUT (HZ * 50) | #define I40E_HEARTBEAT_TIMEOUT (HZ * 50) | ||||
/* Max default timeout in ms, */ | /* Max default timeout in ms, */ | ||||
#define I40E_MAX_NVM_TIMEOUT 18000 | #define I40E_MAX_NVM_TIMEOUT 18000 | ||||
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#define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) | #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) | ||||
#define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) | #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) | ||||
#define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) | #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) | ||||
#define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) | #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) | ||||
#define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) | #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) | ||||
/* Number of Transmit Descriptors must be a multiple of 8. */ | /* Number of Transmit Descriptors must be a multiple of 32. */ | ||||
#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8 | #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 32 | ||||
/* Number of Receive Descriptors must be a multiple of 32 if | /* Number of Receive Descriptors must be a multiple of 32 if | ||||
* the number of descriptors is greater than 32. | * the number of descriptors is greater than 32. | ||||
*/ | */ | ||||
#define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 | #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 | ||||
#define I40E_DESC_UNUSED(R) \ | #define I40E_DESC_UNUSED(R) \ | ||||
((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ | ||||
(R)->next_to_clean - (R)->next_to_use - 1) | (R)->next_to_clean - (R)->next_to_use - 1) | ||||
Show All 13 Lines | enum i40e_debug_mask { | ||||
I40E_DEBUG_HMC = 0x00000040, | I40E_DEBUG_HMC = 0x00000040, | ||||
I40E_DEBUG_NVM = 0x00000080, | I40E_DEBUG_NVM = 0x00000080, | ||||
I40E_DEBUG_LAN = 0x00000100, | I40E_DEBUG_LAN = 0x00000100, | ||||
I40E_DEBUG_FLOW = 0x00000200, | I40E_DEBUG_FLOW = 0x00000200, | ||||
I40E_DEBUG_DCB = 0x00000400, | I40E_DEBUG_DCB = 0x00000400, | ||||
I40E_DEBUG_DIAG = 0x00000800, | I40E_DEBUG_DIAG = 0x00000800, | ||||
I40E_DEBUG_FD = 0x00001000, | I40E_DEBUG_FD = 0x00001000, | ||||
I40E_DEBUG_IWARP = 0x00F00000, | |||||
I40E_DEBUG_AQ_MESSAGE = 0x01000000, | I40E_DEBUG_AQ_MESSAGE = 0x01000000, | ||||
I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, | I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, | ||||
I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, | I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, | ||||
I40E_DEBUG_AQ_COMMAND = 0x06000000, | I40E_DEBUG_AQ_COMMAND = 0x06000000, | ||||
I40E_DEBUG_AQ = 0x0F000000, | I40E_DEBUG_AQ = 0x0F000000, | ||||
I40E_DEBUG_USER = 0xF0000000, | I40E_DEBUG_USER = 0xF0000000, | ||||
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/* Memcpy types */ | /* Memcpy types */ | ||||
enum i40e_memcpy_type { | enum i40e_memcpy_type { | ||||
I40E_NONDMA_TO_NONDMA = 0, | I40E_NONDMA_TO_NONDMA = 0, | ||||
I40E_NONDMA_TO_DMA, | I40E_NONDMA_TO_DMA, | ||||
I40E_DMA_TO_DMA, | I40E_DMA_TO_DMA, | ||||
I40E_DMA_TO_NONDMA | I40E_DMA_TO_NONDMA | ||||
}; | }; | ||||
/* These are structs for managing the hardware information and the operations. | /* These are structs for managing the hardware information and the operations. | ||||
* The structures of function pointers are filled out at init time when we | * The structures of function pointers are filled out at init time when we | ||||
* know for sure exactly which hardware we're working with. This gives us the | * know for sure exactly which hardware we're working with. This gives us the | ||||
* flexibility of using the same main driver code but adapting to slightly | * flexibility of using the same main driver code but adapting to slightly | ||||
* different hardware needs as new parts are developed. For this architecture, | * different hardware needs as new parts are developed. For this architecture, | ||||
* the Firmware and AdminQ are intended to insulate the driver from most of the | * the Firmware and AdminQ are intended to insulate the driver from most of the | ||||
* future changes, but these structures will also do part of the job. | * future changes, but these structures will also do part of the job. | ||||
*/ | */ | ||||
Show All 37 Lines | enum i40e_vsi_type { | ||||
I40E_VSI_MAIN = 0, | I40E_VSI_MAIN = 0, | ||||
I40E_VSI_VMDQ1 = 1, | I40E_VSI_VMDQ1 = 1, | ||||
I40E_VSI_VMDQ2 = 2, | I40E_VSI_VMDQ2 = 2, | ||||
I40E_VSI_CTRL = 3, | I40E_VSI_CTRL = 3, | ||||
I40E_VSI_FCOE = 4, | I40E_VSI_FCOE = 4, | ||||
I40E_VSI_MIRROR = 5, | I40E_VSI_MIRROR = 5, | ||||
I40E_VSI_SRIOV = 6, | I40E_VSI_SRIOV = 6, | ||||
I40E_VSI_FDIR = 7, | I40E_VSI_FDIR = 7, | ||||
I40E_VSI_IWARP = 8, | |||||
I40E_VSI_TYPE_UNKNOWN | I40E_VSI_TYPE_UNKNOWN | ||||
}; | }; | ||||
enum i40e_queue_type { | enum i40e_queue_type { | ||||
I40E_QUEUE_TYPE_RX = 0, | I40E_QUEUE_TYPE_RX = 0, | ||||
I40E_QUEUE_TYPE_TX, | I40E_QUEUE_TYPE_TX, | ||||
I40E_QUEUE_TYPE_PE_CEQ, | I40E_QUEUE_TYPE_PE_CEQ, | ||||
I40E_QUEUE_TYPE_UNKNOWN | I40E_QUEUE_TYPE_UNKNOWN | ||||
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines | #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 | ||||
/* Cloud filter modes: | /* Cloud filter modes: | ||||
* Mode1: Filter on L4 port only | * Mode1: Filter on L4 port only | ||||
* Mode2: Filter for non-tunneled traffic | * Mode2: Filter for non-tunneled traffic | ||||
* Mode3: Filter for tunnel traffic | * Mode3: Filter for tunnel traffic | ||||
*/ | */ | ||||
#define I40E_CLOUD_FILTER_MODE1 0x6 | #define I40E_CLOUD_FILTER_MODE1 0x6 | ||||
#define I40E_CLOUD_FILTER_MODE2 0x7 | #define I40E_CLOUD_FILTER_MODE2 0x7 | ||||
#define I40E_CLOUD_FILTER_MODE3 0x8 | #define I40E_CLOUD_FILTER_MODE3 0x8 | ||||
#define I40E_SWITCH_MODE_MASK 0xF | |||||
u32 management_mode; | u32 management_mode; | ||||
u32 mng_protocols_over_mctp; | u32 mng_protocols_over_mctp; | ||||
#define I40E_MNG_PROTOCOL_PLDM 0x2 | #define I40E_MNG_PROTOCOL_PLDM 0x2 | ||||
#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 | #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 | ||||
#define I40E_MNG_PROTOCOL_NCSI 0x8 | #define I40E_MNG_PROTOCOL_NCSI 0x8 | ||||
u32 npar_enable; | u32 npar_enable; | ||||
u32 os2bmc; | u32 os2bmc; | ||||
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines | enum i40e_nvmupd_cmd { | ||||
I40E_NVMUPD_WRITE_SA, | I40E_NVMUPD_WRITE_SA, | ||||
I40E_NVMUPD_CSUM_CON, | I40E_NVMUPD_CSUM_CON, | ||||
I40E_NVMUPD_CSUM_SA, | I40E_NVMUPD_CSUM_SA, | ||||
I40E_NVMUPD_CSUM_LCB, | I40E_NVMUPD_CSUM_LCB, | ||||
I40E_NVMUPD_STATUS, | I40E_NVMUPD_STATUS, | ||||
I40E_NVMUPD_EXEC_AQ, | I40E_NVMUPD_EXEC_AQ, | ||||
I40E_NVMUPD_GET_AQ_RESULT, | I40E_NVMUPD_GET_AQ_RESULT, | ||||
I40E_NVMUPD_GET_AQ_EVENT, | I40E_NVMUPD_GET_AQ_EVENT, | ||||
I40E_NVMUPD_FEATURES, | |||||
}; | }; | ||||
enum i40e_nvmupd_state { | enum i40e_nvmupd_state { | ||||
I40E_NVMUPD_STATE_INIT, | I40E_NVMUPD_STATE_INIT, | ||||
I40E_NVMUPD_STATE_READING, | I40E_NVMUPD_STATE_READING, | ||||
I40E_NVMUPD_STATE_WRITING, | I40E_NVMUPD_STATE_WRITING, | ||||
I40E_NVMUPD_STATE_INIT_WAIT, | I40E_NVMUPD_STATE_INIT_WAIT, | ||||
I40E_NVMUPD_STATE_WRITE_WAIT, | I40E_NVMUPD_STATE_WRITE_WAIT, | ||||
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#define I40E_NVM_SNT 0x1 | #define I40E_NVM_SNT 0x1 | ||||
#define I40E_NVM_LCB 0x2 | #define I40E_NVM_LCB 0x2 | ||||
#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) | #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) | ||||
#define I40E_NVM_ERA 0x4 | #define I40E_NVM_ERA 0x4 | ||||
#define I40E_NVM_CSUM 0x8 | #define I40E_NVM_CSUM 0x8 | ||||
#define I40E_NVM_AQE 0xe | #define I40E_NVM_AQE 0xe | ||||
#define I40E_NVM_EXEC 0xf | #define I40E_NVM_EXEC 0xf | ||||
#define I40E_NVM_EXEC_GET_AQ_RESULT 0x0 | |||||
#define I40E_NVM_EXEC_FEATURES 0xe | |||||
#define I40E_NVM_EXEC_STATUS 0xf | |||||
#define I40E_NVM_ADAPT_SHIFT 16 | #define I40E_NVM_ADAPT_SHIFT 16 | ||||
#define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) | #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) | ||||
#define I40E_NVMUPD_MAX_DATA 4096 | #define I40E_NVMUPD_MAX_DATA 4096 | ||||
#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ | #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ | ||||
struct i40e_nvm_access { | struct i40e_nvm_access { | ||||
u32 command; | u32 command; | ||||
u32 config; | u32 config; | ||||
u32 offset; /* in bytes */ | u32 offset; /* in bytes */ | ||||
u32 data_size; /* in bytes */ | u32 data_size; /* in bytes */ | ||||
u8 data[1]; | u8 data[1]; | ||||
}; | }; | ||||
/* NVMUpdate features API */ | |||||
#define I40E_NVMUPD_FEATURES_API_VER_MAJOR 0 | |||||
#define I40E_NVMUPD_FEATURES_API_VER_MINOR 14 | |||||
#define I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12 | |||||
#define I40E_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0) | |||||
struct i40e_nvmupd_features { | |||||
u8 major; | |||||
u8 minor; | |||||
u16 size; | |||||
u8 features[I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN]; | |||||
}; | |||||
/* (Q)SFP module access definitions */ | /* (Q)SFP module access definitions */ | ||||
#define I40E_I2C_EEPROM_DEV_ADDR 0xA0 | #define I40E_I2C_EEPROM_DEV_ADDR 0xA0 | ||||
#define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 | #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 | ||||
#define I40E_MODULE_TYPE_ADDR 0x00 | #define I40E_MODULE_TYPE_ADDR 0x00 | ||||
#define I40E_MODULE_REVISION_ADDR 0x01 | #define I40E_MODULE_REVISION_ADDR 0x01 | ||||
#define I40E_MODULE_SFF_8472_COMP 0x5E | #define I40E_MODULE_SFF_8472_COMP 0x5E | ||||
#define I40E_MODULE_SFF_8472_SWAP 0x5C | #define I40E_MODULE_SFF_8472_SWAP 0x5C | ||||
#define I40E_MODULE_SFF_ADDR_MODE 0x04 | #define I40E_MODULE_SFF_ADDR_MODE 0x04 | ||||
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines | struct i40e_hw { | ||||
/* WoL and proxy support */ | /* WoL and proxy support */ | ||||
u16 num_wol_proxy_filters; | u16 num_wol_proxy_filters; | ||||
u16 wol_proxy_vsi_seid; | u16 wol_proxy_vsi_seid; | ||||
#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) | #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) | ||||
#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) | #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) | ||||
#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) | #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) | ||||
#define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) | #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) | ||||
#define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4) | |||||
#define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5) | |||||
#define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6) | |||||
#define I40E_HW_FLAG_DROP_MODE BIT_ULL(7) | |||||
#define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8) | |||||
u64 flags; | u64 flags; | ||||
/* Used in set switch config AQ command */ | /* Used in set switch config AQ command */ | ||||
u16 switch_tag; | u16 switch_tag; | ||||
u16 first_tag; | u16 first_tag; | ||||
u16 second_tag; | u16 second_tag; | ||||
/* NVMUpdate features */ | |||||
struct i40e_nvmupd_features nvmupd_features; | |||||
/* debug mask */ | /* debug mask */ | ||||
u32 debug_mask; | u32 debug_mask; | ||||
char err_str[16]; | char err_str[16]; | ||||
}; | }; | ||||
static INLINE bool i40e_is_vf(struct i40e_hw *hw) | static INLINE bool i40e_is_vf(struct i40e_hw *hw) | ||||
{ | { | ||||
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