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lib/msun/powerpc/fenv.h
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* | * | ||||
* $FreeBSD$ | * $FreeBSD$ | ||||
*/ | */ | ||||
#ifndef _FENV_H_ | #ifndef _FENV_H_ | ||||
#define _FENV_H_ | #define _FENV_H_ | ||||
#include <sys/_types.h> | #include <sys/_types.h> | ||||
#include <machine/endian.h> | |||||
#ifndef __fenv_static | #ifndef __fenv_static | ||||
#define __fenv_static static | #define __fenv_static static | ||||
#endif | #endif | ||||
typedef __uint32_t fenv_t; | typedef __uint32_t fenv_t; | ||||
typedef __uint32_t fexcept_t; | typedef __uint32_t fexcept_t; | ||||
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines | |||||
/* We need to be able to map status flag positions to mask flag positions */ | /* We need to be able to map status flag positions to mask flag positions */ | ||||
#define _FPUSW_SHIFT 22 | #define _FPUSW_SHIFT 22 | ||||
#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ | #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ | ||||
FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) | FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) | ||||
#ifndef _SOFT_FLOAT | #ifndef _SOFT_FLOAT | ||||
#ifdef __SPE__ | #ifdef __SPE__ | ||||
#define __mffs(__env) __asm __volatile("mfspr %0, 512" : "=r" (*(__env))) | #define __mffs(__env) \ | ||||
#define __mtfsf(__env) __asm __volatile("mtspr 512,%0" : : "r" (__env)) | __asm __volatile("mfspr %0, 512" : "=r" ((__env)->__bits.__reg)) | ||||
#define __mtfsf(__env) \ | |||||
__asm __volatile("mtspr 512,%0;isync" :: "r" ((__env).__bits.__reg)) | |||||
#else | #else | ||||
jhibbits: I think these need line wrapped. | |||||
#define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) | #define __mffs(__env) \ | ||||
#define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) | __asm __volatile("mffs %0" : "=f" ((__env)->__d)) | ||||
#define __mtfsf(__env) \ | |||||
__asm __volatile("mtfsf 255,%0" :: "f" ((__env).__d)) | |||||
#endif | #endif | ||||
#else | #else | ||||
#define __mffs(__env) | #define __mffs(__env) | ||||
#define __mtfsf(__env) | #define __mtfsf(__env) | ||||
#endif | #endif | ||||
union __fpscr { | union __fpscr { | ||||
double __d; | double __d; | ||||
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__fenv_static inline int | __fenv_static inline int | ||||
feclearexcept(int __excepts) | feclearexcept(int __excepts) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
if (__excepts & FE_INVALID) | if (__excepts & FE_INVALID) | ||||
__excepts |= FE_ALL_INVALID; | __excepts |= FE_ALL_INVALID; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
__r.__bits.__reg &= ~__excepts; | __r.__bits.__reg &= ~__excepts; | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fegetexceptflag(fexcept_t *__flagp, int __excepts) | fegetexceptflag(fexcept_t *__flagp, int __excepts) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
*__flagp = __r.__bits.__reg & __excepts; | *__flagp = __r.__bits.__reg & __excepts; | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fesetexceptflag(const fexcept_t *__flagp, int __excepts) | fesetexceptflag(const fexcept_t *__flagp, int __excepts) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
if (__excepts & FE_INVALID) | if (__excepts & FE_INVALID) | ||||
__excepts |= FE_ALL_EXCEPT; | __excepts |= FE_ALL_EXCEPT; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
__r.__bits.__reg &= ~__excepts; | __r.__bits.__reg &= ~__excepts; | ||||
__r.__bits.__reg |= *__flagp & __excepts; | __r.__bits.__reg |= *__flagp & __excepts; | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
feraiseexcept(int __excepts) | feraiseexcept(int __excepts) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
if (__excepts & FE_INVALID) | if (__excepts & FE_INVALID) | ||||
__excepts |= FE_VXSOFT; | __excepts |= FE_VXSOFT; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
__r.__bits.__reg |= __excepts; | __r.__bits.__reg |= __excepts; | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fetestexcept(int __excepts) | fetestexcept(int __excepts) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
return (__r.__bits.__reg & __excepts); | return (__r.__bits.__reg & __excepts); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fegetround(void) | fegetround(void) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
return (__r.__bits.__reg & _ROUND_MASK); | return (__r.__bits.__reg & _ROUND_MASK); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fesetround(int __round) | fesetround(int __round) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
if (__round & ~_ROUND_MASK) | if (__round & ~_ROUND_MASK) | ||||
return (-1); | return (-1); | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
__r.__bits.__reg &= ~_ROUND_MASK; | __r.__bits.__reg &= ~_ROUND_MASK; | ||||
__r.__bits.__reg |= __round; | __r.__bits.__reg |= __round; | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fegetenv(fenv_t *__envp) | fegetenv(fenv_t *__envp) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
*__envp = __r.__bits.__reg; | *__envp = __r.__bits.__reg; | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
feholdexcept(fenv_t *__envp) | feholdexcept(fenv_t *__envp) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
*__envp = __r.__d; | *__envp = __r.__d; | ||||
__r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); | __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fesetenv(const fenv_t *__envp) | fesetenv(const fenv_t *__envp) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__r.__bits.__reg = *__envp; | __r.__bits.__reg = *__envp; | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
feupdateenv(const fenv_t *__envp) | feupdateenv(const fenv_t *__envp) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
__r.__bits.__reg &= FE_ALL_EXCEPT; | __r.__bits.__reg &= FE_ALL_EXCEPT; | ||||
__r.__bits.__reg |= *__envp; | __r.__bits.__reg |= *__envp; | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
#if __BSD_VISIBLE | #if __BSD_VISIBLE | ||||
/* We currently provide no external definitions of the functions below. */ | /* We currently provide no external definitions of the functions below. */ | ||||
static inline int | static inline int | ||||
feenableexcept(int __mask) | feenableexcept(int __mask) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
fenv_t __oldmask; | fenv_t __oldmask; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
__oldmask = __r.__bits.__reg; | __oldmask = __r.__bits.__reg; | ||||
__r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; | __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); | return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); | ||||
} | } | ||||
static inline int | static inline int | ||||
fedisableexcept(int __mask) | fedisableexcept(int __mask) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
fenv_t __oldmask; | fenv_t __oldmask; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
__oldmask = __r.__bits.__reg; | __oldmask = __r.__bits.__reg; | ||||
__r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); | __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); | ||||
__mtfsf(__r.__d); | __mtfsf(__r); | ||||
return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); | return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); | ||||
} | } | ||||
static inline int | static inline int | ||||
fegetexcept(void) | fegetexcept(void) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__mffs(&__r.__d); | __mffs(&__r); | ||||
return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); | return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); | ||||
} | } | ||||
#endif /* __BSD_VISIBLE */ | #endif /* __BSD_VISIBLE */ | ||||
__END_DECLS | __END_DECLS | ||||
#endif /* !_FENV_H_ */ | #endif /* !_FENV_H_ */ |
I think these need line wrapped.