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sys/dev/pdc/pdc_regs.h
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/*- | |||||
* Copyright (c) 2019 Juniper Networks, Inc. | |||||
* Copyright (c) 2019 Semihalf. | |||||
* | |||||
* Redistribution and use in source and binary forms, with or without | |||||
* modification, are permitted provided that the following conditions | |||||
* are met: | |||||
* 1. Redistributions of source code must retain the above copyright | |||||
* notice, this list of conditions and the following disclaimer. | |||||
* 2. Redistributions in binary form must reproduce the above copyright | |||||
* notice, this list of conditions and the following disclaimer in the | |||||
* documentation and/or other materials provided with the distribution. | |||||
* | |||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | |||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |||||
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN | |||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |||||
* POSSIBILITY OF SUCH DAMAGE. | |||||
*/ | |||||
#ifndef PDC_REGS_H | |||||
#define PDC_REGS_H | |||||
#include <sys/queue.h> | |||||
#include "pdc.h" | |||||
#define BIT(x) (1 << (x)) | |||||
/* There are four rings, but we support only the first one currently. */ | |||||
#define PDC_RING_COUNT 1 | |||||
#define PDC_MAX_RING_ENTRIES 512 | |||||
#define PDC_MAX_DESC_SIZE 16384 | |||||
#define PDC_MAX_REQUEST_SIZE (BIT(16) - 1) | |||||
#define PDC_RING_MASK (PDC_MAX_RING_ENTRIES-1) | |||||
#define BCM_HDR_LEN 8 | |||||
#define PDC_RING_ENTRY_SIZE sizeof(struct pdc_dma_desc) | |||||
#define RING_ALIGMENT BIT(13) | |||||
#define DATA_ALIGMENT BIT(5) | |||||
#define PDC_DEVCONTROL 0x0 | |||||
#define PDC_DEVSTATUS 0x4 | |||||
#define PDC_BISTSTATUS 0xC | |||||
#define PDC_INTSTATUS 0x20 | |||||
#define PDC_INTMASK 0x24 | |||||
#define PDC_GPTIMER 0x28 | |||||
#define PDC_INTRCVLAZY0 0x30 | |||||
#define PDC_INTRCVLAZY1 0x34 | |||||
#define PDC_INTRCVLAZY2 0x38 | |||||
#define PDC_INTRCVLAZY3 0x3C | |||||
#define PDC_FLOWCNTL_TH 0x104 | |||||
#define PDC_TXARB_WRR_TH 0x108 | |||||
#define PDC_GMACIDLE_CNT_TH 0x10C | |||||
/* We only support Ring 0. */ | |||||
#define PDC_TX_RING 0x200 | |||||
#define PDC_RX_RING 0x220 | |||||
#define PDC_DMA_CTRL 0x0 | |||||
#define PDC_DMA_PTR 0x4 | |||||
#define PDC_DMA_ADDR_LOW 0x8 | |||||
#define PDC_DMA_ADDR_HIGH 0xC | |||||
#define PDC_DMA_STATUS0 0x10 | |||||
#define PDC_DMA_STATUS1 0x14 | |||||
#define PDC_DESCID_MASK 0x1FFF | |||||
#define PDC_DMA_CTRL_ENABLE BIT(0) | |||||
#define PDC_DMA_CTRL_BURST_LEN_OFFSET 18 | |||||
#define PDC_DMA_CTRL_DISABLE_PARITY_CHECK BIT(11) | |||||
#define PDC_DMA_CTRL_RX_RCVOFFSET_OFFSET 1 | |||||
#define PDC_DMA_CTRL_RX_SEPRXHD BIT(9) | |||||
#define PDC_DMA_CTRL_RX_OFLOWCONTINUE BIT(10) | |||||
#define PDC_DMA_CTRL_RX_WAITFORCOMPLETE BIT(12) | |||||
#define PDC_INTMASK_RXINT BIT(16) | |||||
#define PDC_INTMASK_TXINT BIT(24) | |||||
#define PDC_INTRCVLAZY_VALUE ((1 << 24) | 10000) // (Framecount) | Timeout | |||||
#define PDC_DESC_CTRL1_EOT BIT(28) | |||||
#define PDC_DESC_CTRL1_IOC BIT(29) | |||||
#define PDC_DESC_CTRL1_EOF BIT(30) | |||||
#define PDC_DESC_CTRL1_SOF BIT(31) | |||||
#define PDC_INTSTATUS_RX0 BIT(16) | |||||
#define PDC_INTSTATUS_TX0 BIT(24) | |||||
#define PDC_INTSTATUS_DESCPROTERR BIT(12) | |||||
MALLOC_DECLARE(M_PDC); | |||||
MALLOC_DEFINE(M_PDC, "pdc_memory", "memory used by Broadcom PDC"); | |||||
struct pdc_dma_mem { | |||||
bus_dma_segment_t segs[PDC_MAX_RING_ENTRIES / 2]; | |||||
bus_dmamap_t map; | |||||
size_t size; | |||||
int nseg; | |||||
void *vaddr; | |||||
}; | |||||
struct pdc_request_ctx { | |||||
struct pdc_request req; | |||||
struct pdc_sc *sc; | |||||
struct pdc_dma_mem pdc_header; | |||||
struct pdc_dma_mem header; | |||||
struct pdc_dma_mem data; | |||||
struct pdc_dma_mem footer; | |||||
uint32_t rx_desc_id; | |||||
uint32_t rx_desc_count; | |||||
uint32_t tx_desc_id; | |||||
uint32_t tx_desc_count; | |||||
STAILQ_ENTRY(pdc_request_ctx) pdc_ctx_stq; | |||||
}; | |||||
struct pdc_dma_desc { | |||||
uint32_t ctrl1; | |||||
uint32_t ctrl2; | |||||
uint32_t addr_low; | |||||
uint32_t addr_high; | |||||
} __packed; | |||||
struct pdc_ring { | |||||
struct pdc_dma_mem mem; | |||||
struct pdc_dma_desc *desc; | |||||
uint32_t free_desc_id; | |||||
uint32_t free_desc_count; | |||||
}; | |||||
struct pdc_channel { | |||||
struct mtx channel_mtx; | |||||
struct pdc_ring rx; | |||||
struct pdc_ring tx; | |||||
/* Requests that are currently being processed by hw. */ | |||||
STAILQ_HEAD(, pdc_request_ctx) enqueued_requests; | |||||
}; | |||||
struct pdc_sc { | |||||
device_t dev; | |||||
struct resource *mem_res; | |||||
int mem_rid; | |||||
struct resource *irq_res; | |||||
int irq_rid; | |||||
void *intr_cookie; | |||||
uint32_t rx_header_len; | |||||
uint32_t rx_status_len; | |||||
bus_dma_tag_t data_dma_tag; | |||||
bus_dma_tag_t desc_dma_tag; | |||||
bus_dma_tag_t header_dma_tag; | |||||
struct pdc_channel channels[PDC_RING_COUNT]; | |||||
struct pdc_request_ctx requests[PDC_MAX_RING_ENTRIES / 2]; | |||||
/* Pool of requests to use */ | |||||
struct mtx free_requests_mtx; | |||||
STAILQ_HEAD(, pdc_request_ctx) free_requests; | |||||
/* Requests that haven't been enqueued yet. */ | |||||
struct mtx pending_requests_mtx; | |||||
STAILQ_HEAD(, pdc_request_ctx) pending_requests; | |||||
}; | |||||
#endif /* PDC_REGS_H */ |