Differential D3131 Diff 7089 sys/arm64/arm64/gic_v3_its.c

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sys/arm64/arm64/gic_v3_its.c

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines	const char *its_ptab_type[] = {
[GITS_BASER_TYPE_DEV] = "Devices",		[GITS_BASER_TYPE_DEV] = "Devices",
[GITS_BASER_TYPE_VP] = "Virtual Processors",		[GITS_BASER_TYPE_VP] = "Virtual Processors",
[GITS_BASER_TYPE_PP] = "Physical Processors",		[GITS_BASER_TYPE_PP] = "Physical Processors",
[GITS_BASER_TYPE_IC] = "Interrupt Collections",		[GITS_BASER_TYPE_IC] = "Interrupt Collections",
[GITS_BASER_TYPE_RES5] = "Reserved (5)",		[GITS_BASER_TYPE_RES5] = "Reserved (5)",
[GITS_BASER_TYPE_RES6] = "Reserved (6)",		[GITS_BASER_TYPE_RES6] = "Reserved (6)",
[GITS_BASER_TYPE_RES7] = "Reserved (7)",		[GITS_BASER_TYPE_RES7] = "Reserved (7)",
};		};

static struct gic_v3_its_softc *its_sc;		static struct gic_v3_its_softc *its_sc;
		andrewUnsubmitted Done Inline Actions This should have a comment explaining why it's needed. andrew: This should have a comment explaining why it's needed.

#define gic_its_read(sc, len, reg) \		#define gic_its_read(sc, len, reg) \
bus_read_##len(&sc->its_res[0], reg)		bus_read_##len(&sc->its_res[0], reg)

#define gic_its_write(sc, len, reg, val) \		#define gic_its_write(sc, len, reg, val) \
bus_write_##len(&sc->its_res[0], reg, val)		bus_write_##len(&sc->its_res[0], reg, val)

static int		static int
▲ Show 20 Lines • Show All 203 Lines • ▼ Show 20 Lines	for (;;) {
default:		default:
device_printf(sc->dev,		device_printf(sc->dev,
"Unsupported page size: %zuKB\n",		"Unsupported page size: %zuKB\n",
(page_size / 1024));		(page_size / 1024));
its_free_tables(sc);		its_free_tables(sc);
return (ENXIO);		return (ENXIO);
}		}

		/* QUIRK for Cavium ThunderX */
		if (CPU_MATCH(CPU_IMPL_MASK \| CPU_PART_MASK,
		CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)) {
		/*
		* QUIRK: Number of pages that can be set in
		* Thunder's GITS_BASER cannot exceed 0xFD
		*/
		if ((nitspages - 1) > 0xFDUL) {
		device_printf(sc->dev,
		"QUIRK: attempting to configure 0x%lx"
		" pages, reducing to 0xFD\n",
		nitspages);
		nitspages = 0xFDUL;
		}
		}

/* Clear fields under modification first */		/* Clear fields under modification first */
gits_baser &= ~(GITS_BASER_VALID \|		gits_baser &= ~(GITS_BASER_VALID \|
GITS_BASER_CACHE_MASK \| GITS_BASER_TYPE_MASK \|		GITS_BASER_CACHE_MASK \| GITS_BASER_TYPE_MASK \|
GITS_BASER_ESIZE_MASK \| GITS_BASER_PA_MASK \|		GITS_BASER_ESIZE_MASK \| GITS_BASER_PA_MASK \|
GITS_BASER_SHARE_MASK \| GITS_BASER_PSZ_MASK \|		GITS_BASER_SHARE_MASK \| GITS_BASER_PSZ_MASK \|
GITS_BASER_SIZE_MASK);		GITS_BASER_SIZE_MASK);
/* Construct register value */		/* Construct register value */
gits_baser \|=		gits_baser \|=
▲ Show 20 Lines • Show All 987 Lines • ▼ Show 20 Lines	its_device_asign_lpi_locked(struct gic_v3_its_softc *sc,
}		}
*irq = its_dev->lpis.lpi_base + (its_dev->lpis.lpi_num -		*irq = its_dev->lpis.lpi_base + (its_dev->lpis.lpi_num -
its_dev->lpis.lpi_free);		its_dev->lpis.lpi_free);
its_dev->lpis.lpi_free--;		its_dev->lpis.lpi_free--;
}		}
/*		/*
* Message signalled interrupts handling.		* Message signalled interrupts handling.
*/		*/

		zbbAuthorUnsubmitted Done Inline Actions Should be for bootverbose only. zbb: Should be for bootverbose only.
/*		/*
* XXX ARM64TODO: Watch out for "irq" type.		* XXX ARM64TODO: Watch out for "irq" type.
*		*
		andrewUnsubmitted Done Inline Actions How is 13 bits 20MB? andrew: How is 13 bits 20MB?
* In theory GIC can handle up to (2^32 - 1) interrupt IDs whereas		* In theory GIC can handle up to (2^32 - 1) interrupt IDs whereas
* we pass "irq" pointer of type integer. This is obviously wrong but		* we pass "irq" pointer of type integer. This is obviously wrong but
* is determined by the way as PCI layer wants it to be done.		* is determined by the way as PCI layer wants it to be done.
*/		*/
int		int
gic_v3_its_alloc_msix(device_t dev, device_t pci_dev, int *irq)		gic_v3_its_alloc_msix(device_t dev, device_t pci_dev, int *irq)
{		{
struct gic_v3_its_softc *sc;		struct gic_v3_its_softc *sc;
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