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ret		ret

.align 3		.align 3
mair:		mair:
/* Device Normal, no cache Normal, write-back */		/* Device Normal, no cache Normal, write-back */
.quad MAIR_ATTR(0x00, 0) \| MAIR_ATTR(0x44, 1) \| MAIR_ATTR(0xff, 2)		.quad MAIR_ATTR(0x00, 0) \| MAIR_ATTR(0x44, 1) \| MAIR_ATTR(0xff, 2)
tcr:		tcr:
.quad (TCR_TxSZ(64 - VIRT_BITS) \| TCR_ASID_16 \| TCR_TG1_4K)		.quad (TCR_TxSZ(64 - VIRT_BITS) \| TCR_ASID_16 \| TCR_TG1_4K \| \
		TCR_CACHE_ATTRS \| TCR_SMP_ATTRS)
sctlr_set:		sctlr_set:
/* Bits to set */		/* Bits to set */
.quad (SCTLR_UCI \| SCTLR_nTWE \| SCTLR_nTWI \| SCTLR_UCT \| SCTLR_DZE \| \		.quad (SCTLR_UCI \| SCTLR_nTWE \| SCTLR_nTWI \| SCTLR_UCT \| SCTLR_DZE \| \
SCTLR_I \| SCTLR_SED \| SCTLR_C \| SCTLR_M)		SCTLR_I \| SCTLR_SED \| SCTLR_C \| SCTLR_M)
sctlr_clear:		sctlr_clear:
/* Bits to clear */		/* Bits to clear */
.quad (SCTLR_EE \| SCTLR_EOE \| SCTLR_WXN \| SCTLR_UMA \| SCTLR_ITD \| \		.quad (SCTLR_EE \| SCTLR_EOE \| SCTLR_WXN \| SCTLR_UMA \| SCTLR_ITD \| \
SCTLR_THEE \| SCTLR_CP15BEN \| SCTLR_SA0 \| SCTLR_SA \| SCTLR_A)		SCTLR_THEE \| SCTLR_CP15BEN \| SCTLR_SA0 \| SCTLR_SA \| SCTLR_A)
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