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head/sys/dev/smartpqi/smartpqi_sis.c
Show All 38 Lines | db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db, | ||||
LEGACY_SIS_IDBR); | LEGACY_SIS_IDBR); | ||||
db_reg &= ~SIS_ENABLE_MSIX; | db_reg &= ~SIS_ENABLE_MSIX; | ||||
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db, | PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db, | ||||
LEGACY_SIS_IDBR, db_reg); | LEGACY_SIS_IDBR, db_reg); | ||||
DBG_FUNC("OUT\n"); | DBG_FUNC("OUT\n"); | ||||
} | } | ||||
void sis_enable_intx(pqisrc_softstate_t *softs) | |||||
{ | |||||
uint32_t db_reg; | |||||
DBG_FUNC("IN\n"); | |||||
db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db, | |||||
LEGACY_SIS_IDBR); | |||||
db_reg |= SIS_ENABLE_INTX; | |||||
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db, | |||||
LEGACY_SIS_IDBR, db_reg); | |||||
if (pqisrc_sis_wait_for_db_bit_to_clear(softs,SIS_ENABLE_INTX) | |||||
!= PQI_STATUS_SUCCESS) { | |||||
DBG_ERR("Failed to wait for enable intx db bit to clear\n"); | |||||
} | |||||
DBG_FUNC("OUT\n"); | |||||
} | |||||
void sis_disable_intx(pqisrc_softstate_t *softs) | |||||
{ | |||||
uint32_t db_reg; | |||||
DBG_FUNC("IN\n"); | |||||
db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db, | |||||
LEGACY_SIS_IDBR); | |||||
db_reg &= ~SIS_ENABLE_INTX; | |||||
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db, | |||||
LEGACY_SIS_IDBR, db_reg); | |||||
DBG_FUNC("OUT\n"); | |||||
} | |||||
void sis_disable_interrupt(pqisrc_softstate_t *softs) | |||||
{ | |||||
DBG_FUNC("IN"); | |||||
switch(softs->intr_type) { | |||||
case INTR_TYPE_FIXED: | |||||
pqisrc_configure_legacy_intx(softs,false); | |||||
sis_disable_intx(softs); | |||||
break; | |||||
case INTR_TYPE_MSI: | |||||
case INTR_TYPE_MSIX: | |||||
sis_disable_msix(softs); | |||||
break; | |||||
default: | |||||
DBG_ERR("Inerrupt mode none!\n"); | |||||
break; | |||||
} | |||||
DBG_FUNC("OUT"); | |||||
} | |||||
/* Trigger a NMI as part of taking controller offline procedure */ | /* Trigger a NMI as part of taking controller offline procedure */ | ||||
void pqisrc_trigger_nmi_sis(pqisrc_softstate_t *softs) | void pqisrc_trigger_nmi_sis(pqisrc_softstate_t *softs) | ||||
{ | { | ||||
DBG_FUNC("IN\n"); | DBG_FUNC("IN\n"); | ||||
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db, | PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db, | ||||
LEGACY_SIS_IDBR, LE_32(TRIGGER_NMI_SIS)); | LEGACY_SIS_IDBR, LE_32(TRIGGER_NMI_SIS)); | ||||
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | int pqisrc_get_adapter_properties(pqisrc_softstate_t *softs, | ||||
int ret = PQI_STATUS_SUCCESS; | int ret = PQI_STATUS_SUCCESS; | ||||
uint32_t mb[6] = {0}; | uint32_t mb[6] = {0}; | ||||
DBG_FUNC("IN\n"); | DBG_FUNC("IN\n"); | ||||
mb[0] = SIS_CMD_GET_ADAPTER_PROPERTIES; | mb[0] = SIS_CMD_GET_ADAPTER_PROPERTIES; | ||||
ret = pqisrc_send_sis_cmd(softs, mb); | ret = pqisrc_send_sis_cmd(softs, mb); | ||||
if (!ret) { | if (!ret) { | ||||
DBG_INFO("GET_PROPERTIES prop = %x, ext_prop = %x\n", | DBG_INIT("GET_PROPERTIES prop = %x, ext_prop = %x\n", | ||||
mb[1], mb[4]); | mb[1], mb[4]); | ||||
*prop = mb[1]; | *prop = mb[1]; | ||||
*ext_prop = mb[4]; | *ext_prop = mb[4]; | ||||
} | } | ||||
DBG_FUNC("OUT\n"); | DBG_FUNC("OUT\n"); | ||||
return ret; | return ret; | ||||
} | } | ||||
/* Second SIS command to the adapter GET_COMM_PREFERRED_SETTINGS */ | /* Second SIS command to the adapter GET_COMM_PREFERRED_SETTINGS */ | ||||
int pqisrc_get_preferred_settings(pqisrc_softstate_t *softs) | int pqisrc_get_preferred_settings(pqisrc_softstate_t *softs) | ||||
{ | { | ||||
int ret = PQI_STATUS_SUCCESS; | int ret = PQI_STATUS_SUCCESS; | ||||
uint32_t mb[6] = {0}; | uint32_t mb[6] = {0}; | ||||
DBG_FUNC("IN\n"); | DBG_FUNC("IN\n"); | ||||
mb[0] = SIS_CMD_GET_COMM_PREFERRED_SETTINGS; | mb[0] = SIS_CMD_GET_COMM_PREFERRED_SETTINGS; | ||||
ret = pqisrc_send_sis_cmd(softs, mb); | ret = pqisrc_send_sis_cmd(softs, mb); | ||||
if (!ret) { | if (!ret) { | ||||
/* 31:16 maximum command size in KB */ | /* 31:16 maximum command size in KB */ | ||||
softs->pref_settings.max_cmd_size = mb[1] >> 16; | softs->pref_settings.max_cmd_size = mb[1] >> 16; | ||||
/* 15:00: Maximum FIB size in bytes */ | /* 15:00: Maximum FIB size in bytes */ | ||||
softs->pref_settings.max_fib_size = mb[1] & 0x0000FFFF; | softs->pref_settings.max_fib_size = mb[1] & 0x0000FFFF; | ||||
DBG_INFO("cmd size = %x, fib size = %x\n", | DBG_INIT("cmd size = %x, fib size = %x\n", | ||||
softs->pref_settings.max_cmd_size, | softs->pref_settings.max_cmd_size, | ||||
softs->pref_settings.max_fib_size); | softs->pref_settings.max_fib_size); | ||||
} | } | ||||
DBG_FUNC("OUT\n"); | DBG_FUNC("OUT\n"); | ||||
return ret; | return ret; | ||||
} | } | ||||
/* Get supported PQI capabilities from the adapter */ | /* Get supported PQI capabilities from the adapter */ | ||||
int pqisrc_get_sis_pqi_cap(pqisrc_softstate_t *softs) | int pqisrc_get_sis_pqi_cap(pqisrc_softstate_t *softs) | ||||
{ | { | ||||
int ret = PQI_STATUS_SUCCESS; | int ret = PQI_STATUS_SUCCESS; | ||||
uint32_t mb[6] = {0}; | uint32_t mb[6] = {0}; | ||||
DBG_FUNC("IN\n"); | DBG_FUNC("IN\n"); | ||||
mb[0] = SIS_CMD_GET_PQI_CAPABILITIES; | mb[0] = SIS_CMD_GET_PQI_CAPABILITIES; | ||||
ret = pqisrc_send_sis_cmd(softs, mb); | ret = pqisrc_send_sis_cmd(softs, mb); | ||||
if (!ret) { | if (!ret) { | ||||
softs->pqi_cap.max_sg_elem = mb[1]; | softs->pqi_cap.max_sg_elem = mb[1]; | ||||
softs->pqi_cap.max_transfer_size = mb[2]; | softs->pqi_cap.max_transfer_size = mb[2]; | ||||
softs->pqi_cap.max_outstanding_io = mb[3]; | softs->pqi_cap.max_outstanding_io = mb[3]; | ||||
#ifdef DMA_ATTR | |||||
softs->os_specific.buf_dma_attr.dma_attr_sgllen = | |||||
softs->pqi_cap.max_sg_elem; | |||||
softs->os_specific.buf_dma_attr.dma_attr_maxxfer = | |||||
softs->pqi_cap.max_transfer_size; | |||||
softs->os_specific.buf_dma_attr.dma_attr_count_max = | |||||
softs->pqi_cap.max_transfer_size - 1; | |||||
#endif | |||||
softs->pqi_cap.conf_tab_off = mb[4]; | softs->pqi_cap.conf_tab_off = mb[4]; | ||||
softs->pqi_cap.conf_tab_sz = mb[5]; | softs->pqi_cap.conf_tab_sz = mb[5]; | ||||
DBG_INFO("max_sg_elem = %x\n", | DBG_INIT("max_sg_elem = %x\n", | ||||
softs->pqi_cap.max_sg_elem); | softs->pqi_cap.max_sg_elem); | ||||
DBG_INFO("max_transfer_size = %x\n", | DBG_INIT("max_transfer_size = %x\n", | ||||
softs->pqi_cap.max_transfer_size); | softs->pqi_cap.max_transfer_size); | ||||
DBG_INFO("max_outstanding_io = %x\n", | DBG_INIT("max_outstanding_io = %x\n", | ||||
softs->pqi_cap.max_outstanding_io); | softs->pqi_cap.max_outstanding_io); | ||||
} | } | ||||
DBG_FUNC("OUT\n"); | DBG_FUNC("OUT\n"); | ||||
return ret; | return ret; | ||||
} | } | ||||
/* Send INIT STRUCT BASE ADDR - one of the SIS command */ | /* Send INIT STRUCT BASE ADDR - one of the SIS command */ | ||||
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines | int pqisrc_sis_init(pqisrc_softstate_t *softs) | ||||
/* Get PQI settings , 3000h*/ | /* Get PQI settings , 3000h*/ | ||||
ret = pqisrc_get_sis_pqi_cap(softs); | ret = pqisrc_get_sis_pqi_cap(softs); | ||||
if (ret) { | if (ret) { | ||||
DBG_ERR("Failed to get PQI Capabilities\n"); | DBG_ERR("Failed to get PQI Capabilities\n"); | ||||
goto err_out; | goto err_out; | ||||
} | } | ||||
/* We need to allocate DMA memory here , | |||||
* Do any os specific DMA setup. | |||||
*/ | |||||
ret = os_dma_setup(softs); | |||||
if (ret) { | |||||
DBG_ERR("Failed to Setup DMA\n"); | |||||
goto err_out; | |||||
} | |||||
/* Init struct base addr */ | /* Init struct base addr */ | ||||
ret = pqisrc_init_struct_base(softs); | ret = pqisrc_init_struct_base(softs); | ||||
if (ret) { | if (ret) { | ||||
DBG_ERR("Failed to set init struct base addr\n"); | DBG_ERR("Failed to set init struct base addr\n"); | ||||
goto err_dma; | goto err_out; | ||||
} | } | ||||
DBG_FUNC("OUT\n"); | DBG_FUNC("OUT\n"); | ||||
return ret; | return ret; | ||||
err_dma: | |||||
os_dma_destroy(softs); | |||||
err_out: | err_out: | ||||
DBG_FUNC("OUT failed\n"); | DBG_FUNC("OUT failed\n"); | ||||
return ret; | return ret; | ||||
} | } | ||||
/* Deallocate the resources used during SIS initialization */ | /* Deallocate the resources used during SIS initialization */ | ||||
void pqisrc_sis_uninit(pqisrc_softstate_t *softs) | void pqisrc_sis_uninit(pqisrc_softstate_t *softs) | ||||
{ | { | ||||
DBG_FUNC("IN\n"); | DBG_FUNC("IN\n"); | ||||
os_dma_mem_free(softs, &softs->err_buf_dma_mem); | os_dma_mem_free(softs, &softs->err_buf_dma_mem); | ||||
os_dma_destroy(softs); | |||||
os_resource_free(softs); | os_resource_free(softs); | ||||
pqi_reset(softs); | pqi_reset(softs); | ||||
DBG_FUNC("OUT\n"); | DBG_FUNC("OUT\n"); | ||||
} | } | ||||
int pqisrc_sis_wait_for_db_bit_to_clear(pqisrc_softstate_t *softs, uint32_t bit) | int pqisrc_sis_wait_for_db_bit_to_clear(pqisrc_softstate_t *softs, uint32_t bit) | ||||
{ | { | ||||
int rcode = PQI_STATUS_SUCCESS; | int rcode = PQI_STATUS_SUCCESS; | ||||
uint32_t db_reg; | uint32_t db_reg; | ||||
Show All 26 Lines |