Differential D15492 Diff 42754 sys/powerpc/include/spr.h

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sys/powerpc/include/spr.h

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	#define FSL_E500mc 0x8023			#define FSL_E500mc 0x8023
	#define FSL_E5500 0x8024			#define FSL_E5500 0x8024
	#define FSL_E6500 0x8040			#define FSL_E6500 0x8040
	#define FSL_E300C1 0x8083			#define FSL_E300C1 0x8083
	#define FSL_E300C2 0x8084			#define FSL_E300C2 0x8084
	#define FSL_E300C3 0x8085			#define FSL_E300C3 0x8085
	#define FSL_E300C4 0x8086			#define FSL_E300C4 0x8086

	#define SPR_LPCR 0x13e /* Logical Partitioning Control */
	#define LPCR_LPES 0x008 /* Bit 60 */
	#define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */
	#define LPCR_PECE_HDRBL (1ULL << 15) /* Directed Hypervisor Doorbell */
	#define LPCR_PECE_EXT (1ULL << 14) /* External exceptions */
	#define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */
	#define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */
	/* Maintenance exceptions */
	#define LPCR_PECE_WAKESET (LPCR_PECE_EXT \| LPCR_PECE_DECR \| LPCR_PECE_ME)			#define LPCR_PECE_WAKESET (LPCR_PECE_EXT \| LPCR_PECE_DECR \| LPCR_PECE_ME)

	#define SPR_EPCR 0x133			#define SPR_EPCR 0x133
	#define EPCR_EXTGS 0x80000000			#define EPCR_EXTGS 0x80000000
	#define EPCR_DTLBGS 0x40000000			#define EPCR_DTLBGS 0x40000000
	#define EPCR_ITLBGS 0x20000000			#define EPCR_ITLBGS 0x20000000
	#define EPCR_DSIGS 0x10000000			#define EPCR_DSIGS 0x10000000
	#define EPCR_ISIGS 0x08000000			#define EPCR_ISIGS 0x08000000
	#define EPCR_DUVGS 0x04000000			#define EPCR_DUVGS 0x04000000
	#define EPCR_ICM 0x02000000			#define EPCR_ICM 0x02000000
	#define EPCR_GICMGS 0x01000000			#define EPCR_GICMGS 0x01000000
	#define EPCR_DGTMI 0x00800000			#define EPCR_DGTMI 0x00800000
	#define EPCR_DMIUH 0x00400000			#define EPCR_DMIUH 0x00400000
	#define EPCR_PMGS 0x00200000			#define EPCR_PMGS 0x00200000
	#define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */			#define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */

	#define SPR_HSRR0 0x13a			#define SPR_HSRR0 0x13a
	#define SPR_HSRR1 0x13b			#define SPR_HSRR1 0x13b
	#define SPR_LPCR 0x13e /* Logical Partitioning Control */			#define SPR_LPCR 0x13e /* Logical Partitioning Control */
	#define LPCR_LPES 0x008 /* Bit 60 */			#define LPCR_LPES 0x008 /* Bit 60 */
				#define LPCR_HVICE 0x002 /* Hypervisor Virtualization Interrupt (Arch 3.0) */
				nwhitehornUnsubmitted Not Done Inline Actions Note that this is only in ISA >= 3? nwhitehorn: Note that this is only in ISA >= 3?
				jhibbitsAuthorUnsubmitted Not Done Inline Actions Can do, will do jhibbits: Can do, will do
				#define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */
				#define LPCR_PECE_HDRBL (1ULL << 15) /* Directed Hypervisor Doorbell */
				#define LPCR_PECE_EXT (1ULL << 14) /* External exceptions */
				#define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */
				#define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */
				/* Maintenance exceptions */
	#define SPR_LPID 0x13f /* Logical Partitioning Control */			#define SPR_LPID 0x13f /* Logical Partitioning Control */

	#define SPR_PTCR 0x1d0 /* Partition Table Control Register */			#define SPR_PTCR 0x1d0 /* Partition Table Control Register */
	#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */			#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
	#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */			#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */
	#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */			#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */
	#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */			#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */
	#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */			#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */
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