Page MenuHomeFreeBSD
Differential D15492 Diff 42751 sys/powerpc/aim/mp_cpudep.c

Changeset View

Standalone View

View Options

sys/powerpc/aim/mp_cpudep.c

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines if (mfmsr() & PSL_HV) {
isync(); isync();
/* /*
* Direct interrupts to SRR instead of HSRR and * Direct interrupts to SRR instead of HSRR and
* reset LPCR otherwise * reset LPCR otherwise
*/ */
mtspr(SPR_LPID, 0); mtspr(SPR_LPID, 0);
isync(); isync();
mtspr(SPR_LPCR, LPCR_LPES); mtspr(SPR_LPCR, lpcr);
nwhitehornUnsubmitted
Not Done
Inline Actions

HVICE is a reserved bit on POWER8 (ISA 2.07) and should be set only on POWER9 (Power ISA 3+). This should probably be some switch on the ISA version from CPU features rather than the PVR, anyway.

nwhitehorn: HVICE is a reserved bit on POWER8 (ISA 2.07) and should be set only on POWER9 (Power ISA 3+).
jhibbitsAuthorUnsubmitted
Not Done
Inline Actions

Easy enough to address. I'll set up a 'lpcr' variable at platform init time appropriate for the CPU (can use cpu_featuers at this point, since it's initialized much earlier than platform)

jhibbits: Easy enough to address. I'll set up a 'lpcr' variable at platform init time appropriate for…
isync(); isync();
} }
#endif #endif
break; break;
} }
__asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu)); __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
powerpc_sync(); powerpc_sync();
▲ Show 20 Lines • Show All 288 Lines • ▼ Show 20 Lines case MPC7457:
break; break;
case IBMPOWER7: case IBMPOWER7:
case IBMPOWER7PLUS: case IBMPOWER7PLUS:
case IBMPOWER8: case IBMPOWER8:
case IBMPOWER8E: case IBMPOWER8E:
case IBMPOWER9: case IBMPOWER9:
#ifdef __powerpc64__ #ifdef __powerpc64__
if (mfmsr() & PSL_HV) { if (mfmsr() & PSL_HV) {
mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_LPES | mtspr(SPR_LPCR, mfspr(SPR_LPCR) | lpcr |
LPCR_PECE_WAKESET); LPCR_PECE_WAKESET);
isync(); isync();
nwhitehornUnsubmitted
Not Done
Inline Actions

Ditto here with respect to POWER8.

nwhitehorn: Ditto here with respect to POWER8.
} }
#endif #endif
break; break;
default: default:
#ifdef __powerpc64__ #ifdef __powerpc64__
if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */ if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */
break; break;
#endif #endif
printf("WARNING: Unknown CPU type. Cache performace may be " printf("WARNING: Unknown CPU type. Cache performace may be "
"suboptimal.\n"); "suboptimal.\n");
break; break;
} }
} }