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sys/dev/ixl/i40e_type.h
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2013-2015, Intel Corporation | Copyright (c) 2013-2017, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
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#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 | #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 | ||||
/* something less than 1 minute */ | /* something less than 1 minute */ | ||||
#define I40E_HEARTBEAT_TIMEOUT (HZ * 50) | #define I40E_HEARTBEAT_TIMEOUT (HZ * 50) | ||||
/* Max default timeout in ms, */ | /* Max default timeout in ms, */ | ||||
#define I40E_MAX_NVM_TIMEOUT 18000 | #define I40E_MAX_NVM_TIMEOUT 18000 | ||||
/* Max timeout in ms for the phy to respond */ | |||||
#define I40E_MAX_PHY_TIMEOUT 500 | |||||
/* Check whether address is multicast. */ | /* Check whether address is multicast. */ | ||||
#define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) | #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) | ||||
/* Check whether an address is broadcast. */ | /* Check whether an address is broadcast. */ | ||||
#define I40E_IS_BROADCAST(address) \ | #define I40E_IS_BROADCAST(address) \ | ||||
((((u8 *)(address))[0] == ((u8)0xff)) && \ | ((((u8 *)(address))[0] == ((u8)0xff)) && \ | ||||
(((u8 *)(address))[1] == ((u8)0xff))) | (((u8 *)(address))[1] == ((u8)0xff))) | ||||
/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ | /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ | ||||
#define I40E_MS_TO_GTIME(time) ((time) * 1000) | #define I40E_MS_TO_GTIME(time) ((time) * 1000) | ||||
/* forward declaration */ | /* forward declaration */ | ||||
struct i40e_hw; | struct i40e_hw; | ||||
typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); | typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); | ||||
#define I40E_ETH_LENGTH_OF_ADDRESS 6 | #define ETH_ALEN 6 | ||||
/* Data type manipulation macros. */ | /* Data type manipulation macros. */ | ||||
#define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) | #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) | ||||
#define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) | #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) | ||||
#define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) | #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) | ||||
#define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) | #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) | ||||
#define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) | #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) | ||||
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/* Memcpy types */ | /* Memcpy types */ | ||||
enum i40e_memcpy_type { | enum i40e_memcpy_type { | ||||
I40E_NONDMA_TO_NONDMA = 0, | I40E_NONDMA_TO_NONDMA = 0, | ||||
I40E_NONDMA_TO_DMA, | I40E_NONDMA_TO_DMA, | ||||
I40E_DMA_TO_DMA, | I40E_DMA_TO_DMA, | ||||
I40E_DMA_TO_NONDMA | I40E_DMA_TO_NONDMA | ||||
}; | }; | ||||
#define I40E_FW_API_VERSION_MINOR_X722 0x0005 | |||||
#define I40E_FW_API_VERSION_MINOR_X710 0x0005 | |||||
/* These are structs for managing the hardware information and the operations. | /* These are structs for managing the hardware information and the operations. | ||||
* The structures of function pointers are filled out at init time when we | * The structures of function pointers are filled out at init time when we | ||||
* know for sure exactly which hardware we're working with. This gives us the | * know for sure exactly which hardware we're working with. This gives us the | ||||
* flexibility of using the same main driver code but adapting to slightly | * flexibility of using the same main driver code but adapting to slightly | ||||
* different hardware needs as new parts are developed. For this architecture, | * different hardware needs as new parts are developed. For this architecture, | ||||
* the Firmware and AdminQ are intended to insulate the driver from most of the | * the Firmware and AdminQ are intended to insulate the driver from most of the | ||||
* future changes, but these structures will also do part of the job. | * future changes, but these structures will also do part of the job. | ||||
*/ | */ | ||||
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines | enum i40e_queue_type { | ||||
I40E_QUEUE_TYPE_UNKNOWN | I40E_QUEUE_TYPE_UNKNOWN | ||||
}; | }; | ||||
struct i40e_link_status { | struct i40e_link_status { | ||||
enum i40e_aq_phy_type phy_type; | enum i40e_aq_phy_type phy_type; | ||||
enum i40e_aq_link_speed link_speed; | enum i40e_aq_link_speed link_speed; | ||||
u8 link_info; | u8 link_info; | ||||
u8 an_info; | u8 an_info; | ||||
u8 req_fec_info; | |||||
u8 fec_info; | u8 fec_info; | ||||
u8 ext_info; | u8 ext_info; | ||||
u8 loopback; | u8 loopback; | ||||
/* is Link Status Event notification to SW enabled */ | /* is Link Status Event notification to SW enabled */ | ||||
bool lse_enable; | bool lse_enable; | ||||
u16 max_frame_size; | u16 max_frame_size; | ||||
bool crc_enable; | bool crc_enable; | ||||
u8 pacing; | u8 pacing; | ||||
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#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ | #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ | #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ | #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ | #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ | |||||
I40E_PHY_TYPE_OFFSET) | |||||
#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ | |||||
I40E_PHY_TYPE_OFFSET) | |||||
#define I40E_HW_CAP_MAX_GPIO 30 | #define I40E_HW_CAP_MAX_GPIO 30 | ||||
#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 | #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 | ||||
#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 | #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 | ||||
enum i40e_acpi_programming_method { | enum i40e_acpi_programming_method { | ||||
I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, | I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, | ||||
I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 | I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 | ||||
}; | }; | ||||
#define I40E_WOL_SUPPORT_MASK 0x1 | #define I40E_WOL_SUPPORT_MASK 0x1 | ||||
#define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2 | #define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2 | ||||
#define I40E_PROXY_SUPPORT_MASK 0x4 | #define I40E_PROXY_SUPPORT_MASK 0x4 | ||||
/* Capabilities of a PF or a VF or the whole device */ | /* Capabilities of a PF or a VF or the whole device */ | ||||
struct i40e_hw_capabilities { | struct i40e_hw_capabilities { | ||||
u32 switch_mode; | u32 switch_mode; | ||||
#define I40E_NVM_IMAGE_TYPE_EVB 0x0 | #define I40E_NVM_IMAGE_TYPE_EVB 0x0 | ||||
#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 | #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 | ||||
#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 | #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 | ||||
/* Cloud filter modes: | |||||
* Mode1: Filter on L4 port only | |||||
* Mode2: Filter for non-tunneled traffic | |||||
* Mode3: Filter for tunnel traffic | |||||
*/ | |||||
#define I40E_CLOUD_FILTER_MODE1 0x6 | |||||
#define I40E_CLOUD_FILTER_MODE2 0x7 | |||||
#define I40E_CLOUD_FILTER_MODE3 0x8 | |||||
u32 management_mode; | u32 management_mode; | ||||
u32 mng_protocols_over_mctp; | u32 mng_protocols_over_mctp; | ||||
#define I40E_MNG_PROTOCOL_PLDM 0x2 | #define I40E_MNG_PROTOCOL_PLDM 0x2 | ||||
#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 | #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 | ||||
#define I40E_MNG_PROTOCOL_NCSI 0x8 | #define I40E_MNG_PROTOCOL_NCSI 0x8 | ||||
u32 npar_enable; | u32 npar_enable; | ||||
u32 os2bmc; | u32 os2bmc; | ||||
u32 valid_functions; | u32 valid_functions; | ||||
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines | #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 | ||||
u64 wr_csr_prot; | u64 wr_csr_prot; | ||||
bool apm_wol_support; | bool apm_wol_support; | ||||
enum i40e_acpi_programming_method acpi_prog_method; | enum i40e_acpi_programming_method acpi_prog_method; | ||||
bool proxy_support; | bool proxy_support; | ||||
}; | }; | ||||
struct i40e_mac_info { | struct i40e_mac_info { | ||||
enum i40e_mac_type type; | enum i40e_mac_type type; | ||||
u8 addr[I40E_ETH_LENGTH_OF_ADDRESS]; | u8 addr[ETH_ALEN]; | ||||
u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS]; | u8 perm_addr[ETH_ALEN]; | ||||
u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS]; | u8 san_addr[ETH_ALEN]; | ||||
u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS]; | u8 port_addr[ETH_ALEN]; | ||||
u16 max_fcoeq; | u16 max_fcoeq; | ||||
}; | }; | ||||
enum i40e_aq_resources_ids { | enum i40e_aq_resources_ids { | ||||
I40E_NVM_RESOURCE_ID = 1 | I40E_NVM_RESOURCE_ID = 1 | ||||
}; | }; | ||||
enum i40e_aq_resource_access_type { | enum i40e_aq_resource_access_type { | ||||
Show All 25 Lines | enum i40e_nvmupd_cmd { | ||||
I40E_NVMUPD_WRITE_LCB, | I40E_NVMUPD_WRITE_LCB, | ||||
I40E_NVMUPD_WRITE_SA, | I40E_NVMUPD_WRITE_SA, | ||||
I40E_NVMUPD_CSUM_CON, | I40E_NVMUPD_CSUM_CON, | ||||
I40E_NVMUPD_CSUM_SA, | I40E_NVMUPD_CSUM_SA, | ||||
I40E_NVMUPD_CSUM_LCB, | I40E_NVMUPD_CSUM_LCB, | ||||
I40E_NVMUPD_STATUS, | I40E_NVMUPD_STATUS, | ||||
I40E_NVMUPD_EXEC_AQ, | I40E_NVMUPD_EXEC_AQ, | ||||
I40E_NVMUPD_GET_AQ_RESULT, | I40E_NVMUPD_GET_AQ_RESULT, | ||||
I40E_NVMUPD_GET_AQ_EVENT, | |||||
}; | }; | ||||
enum i40e_nvmupd_state { | enum i40e_nvmupd_state { | ||||
I40E_NVMUPD_STATE_INIT, | I40E_NVMUPD_STATE_INIT, | ||||
I40E_NVMUPD_STATE_READING, | I40E_NVMUPD_STATE_READING, | ||||
I40E_NVMUPD_STATE_WRITING, | I40E_NVMUPD_STATE_WRITING, | ||||
I40E_NVMUPD_STATE_INIT_WAIT, | I40E_NVMUPD_STATE_INIT_WAIT, | ||||
I40E_NVMUPD_STATE_WRITE_WAIT, | I40E_NVMUPD_STATE_WRITE_WAIT, | ||||
I40E_NVMUPD_STATE_ERROR | I40E_NVMUPD_STATE_ERROR | ||||
}; | }; | ||||
/* nvm_access definition and its masks/shifts need to be accessible to | /* nvm_access definition and its masks/shifts need to be accessible to | ||||
* application, core driver, and shared code. Where is the right file? | * application, core driver, and shared code. Where is the right file? | ||||
*/ | */ | ||||
#define I40E_NVM_READ 0xB | #define I40E_NVM_READ 0xB | ||||
#define I40E_NVM_WRITE 0xC | #define I40E_NVM_WRITE 0xC | ||||
#define I40E_NVM_MOD_PNT_MASK 0xFF | #define I40E_NVM_MOD_PNT_MASK 0xFF | ||||
#define I40E_NVM_TRANS_SHIFT 8 | #define I40E_NVM_TRANS_SHIFT 8 | ||||
#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) | #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) | ||||
#define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 | |||||
#define I40E_NVM_PRESERVATION_FLAGS_MASK \ | |||||
(0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) | |||||
#define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 | |||||
#define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 | |||||
#define I40E_NVM_CON 0x0 | #define I40E_NVM_CON 0x0 | ||||
#define I40E_NVM_SNT 0x1 | #define I40E_NVM_SNT 0x1 | ||||
#define I40E_NVM_LCB 0x2 | #define I40E_NVM_LCB 0x2 | ||||
#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) | #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) | ||||
#define I40E_NVM_ERA 0x4 | #define I40E_NVM_ERA 0x4 | ||||
#define I40E_NVM_CSUM 0x8 | #define I40E_NVM_CSUM 0x8 | ||||
#define I40E_NVM_AQE 0xe | |||||
#define I40E_NVM_EXEC 0xf | #define I40E_NVM_EXEC 0xf | ||||
#define I40E_NVM_ADAPT_SHIFT 16 | #define I40E_NVM_ADAPT_SHIFT 16 | ||||
#define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) | #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) | ||||
#define I40E_NVMUPD_MAX_DATA 4096 | #define I40E_NVMUPD_MAX_DATA 4096 | ||||
#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ | #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ | ||||
struct i40e_nvm_access { | struct i40e_nvm_access { | ||||
u32 command; | u32 command; | ||||
u32 config; | u32 config; | ||||
u32 offset; /* in bytes */ | u32 offset; /* in bytes */ | ||||
u32 data_size; /* in bytes */ | u32 data_size; /* in bytes */ | ||||
u8 data[1]; | u8 data[1]; | ||||
}; | }; | ||||
/* (Q)SFP module access definitions */ | |||||
#define I40E_I2C_EEPROM_DEV_ADDR 0xA0 | |||||
#define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 | |||||
#define I40E_MODULE_TYPE_ADDR 0x00 | |||||
#define I40E_MODULE_REVISION_ADDR 0x01 | |||||
#define I40E_MODULE_SFF_8472_COMP 0x5E | |||||
#define I40E_MODULE_SFF_8472_SWAP 0x5C | |||||
#define I40E_MODULE_SFF_ADDR_MODE 0x04 | |||||
#define I40E_MODULE_SFF_DIAG_CAPAB 0x40 | |||||
#define I40E_MODULE_TYPE_QSFP_PLUS 0x0D | |||||
#define I40E_MODULE_TYPE_QSFP28 0x11 | |||||
#define I40E_MODULE_QSFP_MAX_LEN 640 | |||||
/* PCI bus types */ | /* PCI bus types */ | ||||
enum i40e_bus_type { | enum i40e_bus_type { | ||||
i40e_bus_type_unknown = 0, | i40e_bus_type_unknown = 0, | ||||
i40e_bus_type_pci, | i40e_bus_type_pci, | ||||
i40e_bus_type_pcix, | i40e_bus_type_pcix, | ||||
i40e_bus_type_pci_express, | i40e_bus_type_pci_express, | ||||
i40e_bus_type_reserved | i40e_bus_type_reserved | ||||
}; | }; | ||||
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines | struct i40e_hw { | ||||
u16 numa_node; | u16 numa_node; | ||||
/* Admin Queue info */ | /* Admin Queue info */ | ||||
struct i40e_adminq_info aq; | struct i40e_adminq_info aq; | ||||
/* state of nvm update process */ | /* state of nvm update process */ | ||||
enum i40e_nvmupd_state nvmupd_state; | enum i40e_nvmupd_state nvmupd_state; | ||||
struct i40e_aq_desc nvm_wb_desc; | struct i40e_aq_desc nvm_wb_desc; | ||||
struct i40e_aq_desc nvm_aq_event_desc; | |||||
struct i40e_virt_mem nvm_buff; | struct i40e_virt_mem nvm_buff; | ||||
bool nvm_release_on_done; | bool nvm_release_on_done; | ||||
u16 nvm_wait_opcode; | u16 nvm_wait_opcode; | ||||
/* HMC info */ | /* HMC info */ | ||||
struct i40e_hmc_info hmc; /* HMC info struct */ | struct i40e_hmc_info hmc; /* HMC info struct */ | ||||
/* LLDP/DCBX Status */ | /* LLDP/DCBX Status */ | ||||
u16 dcbx_status; | u16 dcbx_status; | ||||
/* DCBX info */ | /* DCBX info */ | ||||
struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ | struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ | ||||
struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ | struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ | ||||
struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ | struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ | ||||
/* WoL and proxy support */ | /* WoL and proxy support */ | ||||
u16 num_wol_proxy_filters; | u16 num_wol_proxy_filters; | ||||
u16 wol_proxy_vsi_seid; | u16 wol_proxy_vsi_seid; | ||||
#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) | #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) | ||||
#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) | |||||
#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) | |||||
#define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) | |||||
u64 flags; | u64 flags; | ||||
/* Used in set switch config AQ command */ | |||||
u16 switch_tag; | |||||
u16 first_tag; | |||||
u16 second_tag; | |||||
/* debug mask */ | /* debug mask */ | ||||
u32 debug_mask; | u32 debug_mask; | ||||
char err_str[16]; | char err_str[16]; | ||||
}; | }; | ||||
static INLINE bool i40e_is_vf(struct i40e_hw *hw) | static INLINE bool i40e_is_vf(struct i40e_hw *hw) | ||||
{ | { | ||||
return (hw->mac.type == I40E_MAC_VF || | return (hw->mac.type == I40E_MAC_VF || | ||||
▲ Show 20 Lines • Show All 726 Lines • ▼ Show 20 Lines | |||||
#define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 | #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 | ||||
#define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 | #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 | ||||
#define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 | #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 | ||||
#define I40E_SR_RO_PCIE_LCB_PTR 0x0A | #define I40E_SR_RO_PCIE_LCB_PTR 0x0A | ||||
#define I40E_SR_EMP_IMAGE_PTR 0x0B | #define I40E_SR_EMP_IMAGE_PTR 0x0B | ||||
#define I40E_SR_PE_IMAGE_PTR 0x0C | #define I40E_SR_PE_IMAGE_PTR 0x0C | ||||
#define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D | #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D | ||||
#define I40E_SR_MNG_CONFIG_PTR 0x0E | #define I40E_SR_MNG_CONFIG_PTR 0x0E | ||||
#define I40E_SR_EMP_MODULE_PTR 0x0F | #define I40E_EMP_MODULE_PTR 0x0F | ||||
#define I40E_SR_EMP_MODULE_PTR 0x48 | |||||
#define I40E_SR_PBA_FLAGS 0x15 | #define I40E_SR_PBA_FLAGS 0x15 | ||||
#define I40E_SR_PBA_BLOCK_PTR 0x16 | #define I40E_SR_PBA_BLOCK_PTR 0x16 | ||||
#define I40E_SR_BOOT_CONFIG_PTR 0x17 | #define I40E_SR_BOOT_CONFIG_PTR 0x17 | ||||
#define I40E_NVM_OEM_VER_OFF 0x83 | #define I40E_NVM_OEM_VER_OFF 0x83 | ||||
#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 | #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 | ||||
#define I40E_SR_NVM_WAKE_ON_LAN 0x19 | #define I40E_SR_NVM_WAKE_ON_LAN 0x19 | ||||
#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 | #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 | ||||
#define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 | #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 | ||||
Show All 24 Lines | |||||
#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D | #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D | ||||
#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E | #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E | ||||
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ | /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ | ||||
#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 | #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 | ||||
#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 | #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 | ||||
#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 | #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 | ||||
#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) | #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) | ||||
#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) | |||||
#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) | |||||
#define I40E_PTR_TYPE BIT(15) | |||||
#define I40E_SR_OCP_CFG_WORD0 0x2B | |||||
#define I40E_SR_OCP_ENABLED BIT(15) | |||||
/* Shadow RAM related */ | /* Shadow RAM related */ | ||||
#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 | #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 | ||||
#define I40E_SR_BUF_ALIGNMENT 4096 | #define I40E_SR_BUF_ALIGNMENT 4096 | ||||
#define I40E_SR_WORDS_IN_1KB 512 | #define I40E_SR_WORDS_IN_1KB 512 | ||||
/* Checksum should be calculated such that after adding all the words, | /* Checksum should be calculated such that after adding all the words, | ||||
* including the checksum word itself, the sum should be 0xBABA. | * including the checksum word itself, the sum should be 0xBABA. | ||||
*/ | */ | ||||
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enum i40e_reset_type { | enum i40e_reset_type { | ||||
I40E_RESET_POR = 0, | I40E_RESET_POR = 0, | ||||
I40E_RESET_CORER = 1, | I40E_RESET_CORER = 1, | ||||
I40E_RESET_GLOBR = 2, | I40E_RESET_GLOBR = 2, | ||||
I40E_RESET_EMPR = 3, | I40E_RESET_EMPR = 3, | ||||
}; | }; | ||||
/* IEEE 802.1AB LLDP Agent Variables from NVM */ | /* IEEE 802.1AB LLDP Agent Variables from NVM */ | ||||
#define I40E_NVM_LLDP_CFG_PTR 0xD | #define I40E_NVM_LLDP_CFG_PTR 0x06 | ||||
#define I40E_SR_LLDP_CFG_PTR 0x31 | |||||
struct i40e_lldp_variables { | struct i40e_lldp_variables { | ||||
u16 length; | u16 length; | ||||
u16 adminstatus; | u16 adminstatus; | ||||
u16 msgfasttx; | u16 msgfasttx; | ||||
u16 msgtxinterval; | u16 msgtxinterval; | ||||
u16 txparams; | u16 txparams; | ||||
u16 timers; | u16 timers; | ||||
u16 crc8; | u16 crc8; | ||||
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