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sys/dev/ixl/i40e_adminq.c
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2013-2015, Intel Corporation | Copyright (c) 2013-2017, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
▲ Show 20 Lines • Show All 627 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw) | ||||
hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; | hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; | ||||
i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); | i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); | ||||
i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), | i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), | ||||
&oem_hi); | &oem_hi); | ||||
i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), | i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), | ||||
&oem_lo); | &oem_lo); | ||||
hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; | hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; | ||||
/* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */ | |||||
if ((hw->aq.api_maj_ver > 1) || | |||||
((hw->aq.api_maj_ver == 1) && | |||||
(hw->aq.api_min_ver >= 7))) | |||||
hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; | |||||
if (hw->mac.type == I40E_MAC_XL710 && | |||||
hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && | |||||
hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { | |||||
hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; | |||||
} | |||||
/* Newer versions of firmware require lock when reading the NVM */ | |||||
if ((hw->aq.api_maj_ver > 1) || | |||||
((hw->aq.api_maj_ver == 1) && | |||||
(hw->aq.api_min_ver >= 5))) | |||||
hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; | |||||
if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { | if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { | ||||
ret_code = I40E_ERR_FIRMWARE_API_VERSION; | ret_code = I40E_ERR_FIRMWARE_API_VERSION; | ||||
goto init_adminq_free_arq; | goto init_adminq_free_arq; | ||||
} | } | ||||
/* pre-emptive resource lock release */ | /* pre-emptive resource lock release */ | ||||
i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); | i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); | ||||
hw->nvm_release_on_done = FALSE; | hw->nvm_release_on_done = FALSE; | ||||
▲ Show 20 Lines • Show All 239 Lines • ▼ Show 20 Lines | if (!details->async && !details->postpone) { | ||||
u32 total_delay = 0; | u32 total_delay = 0; | ||||
do { | do { | ||||
/* AQ designers suggest use of head for better | /* AQ designers suggest use of head for better | ||||
* timing reliability than DD bit | * timing reliability than DD bit | ||||
*/ | */ | ||||
if (i40e_asq_done(hw)) | if (i40e_asq_done(hw)) | ||||
break; | break; | ||||
i40e_msec_delay(1); | i40e_usec_delay(50); | ||||
total_delay++; | total_delay += 50; | ||||
} while (total_delay < hw->aq.asq_cmd_timeout); | } while (total_delay < hw->aq.asq_cmd_timeout); | ||||
} | } | ||||
/* if ready, copy the desc back to temp */ | /* if ready, copy the desc back to temp */ | ||||
if (i40e_asq_done(hw)) { | if (i40e_asq_done(hw)) { | ||||
i40e_memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc), | i40e_memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc), | ||||
I40E_DMA_TO_NONDMA); | I40E_DMA_TO_NONDMA); | ||||
if (buff != NULL) | if (buff != NULL) | ||||
Show All 24 Lines | enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw, | ||||
/* save writeback aq if requested */ | /* save writeback aq if requested */ | ||||
if (details->wb_desc) | if (details->wb_desc) | ||||
i40e_memcpy(details->wb_desc, desc_on_ring, | i40e_memcpy(details->wb_desc, desc_on_ring, | ||||
sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA); | sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA); | ||||
/* update the error if time out occurred */ | /* update the error if time out occurred */ | ||||
if ((!cmd_completed) && | if ((!cmd_completed) && | ||||
(!details->async && !details->postpone)) { | (!details->async && !details->postpone)) { | ||||
i40e_debug(hw, | if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { | ||||
I40E_DEBUG_AQ_MESSAGE, | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | ||||
"AQTX: AQ Critical error.\n"); | |||||
status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR; | |||||
} else { | |||||
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | |||||
"AQTX: Writeback timeout.\n"); | "AQTX: Writeback timeout.\n"); | ||||
status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; | status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; | ||||
} | } | ||||
} | |||||
asq_send_command_error: | asq_send_command_error: | ||||
i40e_release_spinlock(&hw->aq.asq_spinlock); | i40e_release_spinlock(&hw->aq.asq_spinlock); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_fill_default_direct_cmd_desc - AQ descriptor helper function | * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function | ||||
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines | if (hw->aq.arq.count == 0) { | ||||
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | ||||
"AQRX: Admin queue not initialized.\n"); | "AQRX: Admin queue not initialized.\n"); | ||||
ret_code = I40E_ERR_QUEUE_EMPTY; | ret_code = I40E_ERR_QUEUE_EMPTY; | ||||
goto clean_arq_element_err; | goto clean_arq_element_err; | ||||
} | } | ||||
/* set next_to_use to head */ | /* set next_to_use to head */ | ||||
if (!i40e_is_vf(hw)) | if (!i40e_is_vf(hw)) | ||||
ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); | ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; | ||||
if (i40e_is_vf(hw)) | else | ||||
ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK); | ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK; | ||||
if (ntu == ntc) { | if (ntu == ntc) { | ||||
/* nothing to do - shouldn't need to update ring's values */ | /* nothing to do - shouldn't need to update ring's values */ | ||||
ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; | ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; | ||||
goto clean_arq_element_out; | goto clean_arq_element_out; | ||||
} | } | ||||
/* now clean the next descriptor */ | /* now clean the next descriptor */ | ||||
desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); | desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); | ||||
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw, | ||||
wr32(hw, hw->aq.arq.tail, ntc); | wr32(hw, hw->aq.arq.tail, ntc); | ||||
/* ntc is updated to tail + 1 */ | /* ntc is updated to tail + 1 */ | ||||
ntc++; | ntc++; | ||||
if (ntc == hw->aq.num_arq_entries) | if (ntc == hw->aq.num_arq_entries) | ||||
ntc = 0; | ntc = 0; | ||||
hw->aq.arq.next_to_clean = ntc; | hw->aq.arq.next_to_clean = ntc; | ||||
hw->aq.arq.next_to_use = ntu; | hw->aq.arq.next_to_use = ntu; | ||||
i40e_nvmupd_check_wait_event(hw, LE16_TO_CPU(e->desc.opcode)); | i40e_nvmupd_check_wait_event(hw, LE16_TO_CPU(e->desc.opcode), &e->desc); | ||||
clean_arq_element_out: | clean_arq_element_out: | ||||
/* Set pending if needed, unlock and return */ | /* Set pending if needed, unlock and return */ | ||||
if (pending != NULL) | if (pending != NULL) | ||||
*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); | *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); | ||||
clean_arq_element_err: | clean_arq_element_err: | ||||
i40e_release_spinlock(&hw->aq.arq_spinlock); | i40e_release_spinlock(&hw->aq.arq_spinlock); | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||