Differential D14501 Diff 39943 sys/amd64/vmm/amd/amdvi_priv.h

Changeset View

Standalone View

sys/amd64/vmm/amd/amdvi_priv.h

	Show First 20 Lines • Show All 349 Lines • ▼ Show 20 Lines
	struct amdvi_domain {			struct amdvi_domain {
	uint64_t ptp; / Highest level page table */			uint64_t ptp; / Highest level page table */
	int ptp_level; /* Level of page tables */			int ptp_level; /* Level of page tables */
	u_int id; /* Domain id */			u_int id; /* Domain id */
	SLIST_ENTRY (amdvi_domain) next;			SLIST_ENTRY (amdvi_domain) next;
	};			};

	/*			/*
				* I/O Virtualization Hardware Definition Block (IVHD) type 0x10 (legacy)
				* uses ACPI_IVRS_HARDWARE define in contrib/dev/acpica/include/actbl2.h
				* New IVHD types 0x11 and 0x40 as defined in AMD IOMMU spec[48882] are missing in
				grehanUnsubmitted Not Done Inline Actions typos: New IVHD types 0x11 and 0x40 as defined grehan: typos: New IVHD types 0x11 and 0x40 as defined
				* ACPI code. These new types add extra field EFR(Extended Feature Register).
				* XXX : Use definition from ACPI when it is available.
				*/
				typedef struct acpi_ivrs_hardware_efr_sup
				{
				ACPI_IVRS_HEADER Header;
				UINT16 CapabilityOffset; /* Offset for IOMMU control fields */
				UINT64 BaseAddress; /* IOMMU control registers */
				UINT16 PciSegmentGroup;
				UINT16 Info; /* MSI number and unit ID */
				UINT32 Attr; /* IOMMU Feature */
				UINT64 ExtFR; /* IOMMU Extended Feature */
				UINT64 Reserved; /* v1 feature or v2 attribute */
				} __attribute__ ((__packed__)) ACPI_IVRS_HARDWARE_EFRSUP;
				CTASSERT(sizeof(ACPI_IVRS_HARDWARE_EFRSUP) == 40);
				grehanUnsubmitted Not Done Inline Actions Should there be a CTASSERT for this struct size ? Looks like it could need to be __packed. grehan: Should there be a CTASSERT for this struct size ? Looks like it could need to be __packed.

				/*
				* Different type of IVHD.
				* XXX: Use AcpiIvrsType once new IVHD types are available.
				*/
				enum IvrsType
				{
				IVRS_TYPE_HARDWARE_LEGACY = 0x10, /* Legacy without EFRi support. */
				IVRS_TYPE_HARDWARE_EFR = 0x11, /* With EFR support. */
				IVRS_TYPE_HARDWARE_MIXED = 0x40, /* Mixed with EFR support. */
				};

				/*
	* AMD IOMMU softc.			* AMD IOMMU softc.
	*/			*/
	struct amdvi_softc {			struct amdvi_softc {
	struct amdvi_ctrl ctrl; / Control area. */			struct amdvi_ctrl ctrl; / Control area. */
	device_t dev; /* IOMMU device. */			device_t dev; /* IOMMU device. */
	enum AcpiIvrsType ivhd_type; /* IOMMU IVHD type 0x10/0x11 or 0x40 */			enum IvrsType ivhd_type; /* IOMMU IVHD type. */
	bool iotlb; /* IOTLB supported by IOMMU */			bool iotlb; /* IOTLB supported by IOMMU */
	struct amdvi_cmd cmd; / Command descriptor area. */			struct amdvi_cmd cmd; / Command descriptor area. */
	int cmd_max; /* Max number of commands. */			int cmd_max; /* Max number of commands. */
	uint64_t cmp_data; /* Command completion write back. */			uint64_t cmp_data; /* Command completion write back. */
	struct amdvi_event event; / Event descriptor area. */			struct amdvi_event event; / Event descriptor area. */
	struct resource event_res; / Event interrupt resource. */			struct resource event_res; / Event interrupt resource. */
	void event_tag; / Event interrupt tag. */			void event_tag; / Event interrupt tag. */
	int event_max; /* Max number of events. */			int event_max; /* Max number of events. */
	Show All 27 Lines