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head/sys/dev/uart/uart_dev_pl011.c
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#include <sys/cdefs.h> | #include <sys/cdefs.h> | ||||
__FBSDID("$FreeBSD$"); | __FBSDID("$FreeBSD$"); | ||||
#include <sys/param.h> | #include <sys/param.h> | ||||
#include <sys/systm.h> | #include <sys/systm.h> | ||||
#include <sys/kernel.h> | #include <sys/kernel.h> | ||||
#include <sys/bus.h> | #include <sys/bus.h> | ||||
#include <machine/bus.h> | #include <machine/bus.h> | ||||
#include <machine/machdep.h> | |||||
#include <dev/uart/uart.h> | #include <dev/uart/uart.h> | ||||
#include <dev/uart/uart_cpu.h> | #include <dev/uart/uart_cpu.h> | ||||
#ifdef FDT | #ifdef FDT | ||||
#include <dev/uart/uart_cpu_fdt.h> | #include <dev/uart/uart_cpu_fdt.h> | ||||
#include <dev/ofw/ofw_bus.h> | #include <dev/ofw/ofw_bus.h> | ||||
#endif | #endif | ||||
#include <dev/uart/uart_bus.h> | #include <dev/uart/uart_bus.h> | ||||
#include "uart_if.h" | #include "uart_if.h" | ||||
#ifdef DEV_ACPI | #ifdef DEV_ACPI | ||||
#include <dev/uart/uart_cpu_acpi.h> | #include <dev/uart/uart_cpu_acpi.h> | ||||
#include <contrib/dev/acpica/include/acpi.h> | #include <contrib/dev/acpica/include/acpi.h> | ||||
#include <contrib/dev/acpica/include/accommon.h> | #include <contrib/dev/acpica/include/accommon.h> | ||||
#include <contrib/dev/acpica/include/actables.h> | #include <contrib/dev/acpica/include/actables.h> | ||||
#endif | #endif | ||||
#include <sys/kdb.h> | #include <sys/kdb.h> | ||||
#ifdef __aarch64__ | |||||
#define IS_FDT (arm64_bus_method == ARM64_BUS_FDT) | |||||
#elif defined(FDT) | |||||
#define IS_FDT 1 | |||||
#else | |||||
#error Unsupported configuration | |||||
#endif | |||||
/* PL011 UART registers and masks*/ | /* PL011 UART registers and masks*/ | ||||
#define UART_DR 0x00 /* Data register */ | #define UART_DR 0x00 /* Data register */ | ||||
#define DR_FE (1 << 8) /* Framing error */ | #define DR_FE (1 << 8) /* Framing error */ | ||||
#define DR_PE (1 << 9) /* Parity error */ | #define DR_PE (1 << 9) /* Parity error */ | ||||
#define DR_BE (1 << 10) /* Break error */ | #define DR_BE (1 << 10) /* Break error */ | ||||
#define DR_OE (1 << 11) /* Overrun error */ | #define DR_OE (1 << 11) /* Overrun error */ | ||||
#define UART_FR 0x06 /* Flag register */ | #define UART_FR 0x06 /* Flag register */ | ||||
▲ Show 20 Lines • Show All 375 Lines • ▼ Show 20 Lines | uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, | ||||
uart_lock(sc->sc_hwmtx); | uart_lock(sc->sc_hwmtx); | ||||
uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); | uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); | ||||
uart_unlock(sc->sc_hwmtx); | uart_unlock(sc->sc_hwmtx); | ||||
return (0); | return (0); | ||||
} | } | ||||
#ifdef FDT | |||||
static int | static int | ||||
uart_pl011_bus_probe(struct uart_softc *sc) | uart_pl011_bus_hwrev_fdt(struct uart_softc *sc) | ||||
{ | { | ||||
uint8_t hwrev; | |||||
#ifdef FDT | |||||
pcell_t node; | pcell_t node; | ||||
uint32_t periphid; | uint32_t periphid; | ||||
/* | /* | ||||
* The FIFO sizes vary depending on hardware; rev 2 and below have 16 | * The FIFO sizes vary depending on hardware; rev 2 and below have 16 | ||||
* byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the | * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the | ||||
* primecell periphid register, but we get a bit of drama, as always, | * primecell periphid register, but we get a bit of drama, as always, | ||||
* with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte | * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte | ||||
* FIFOs. We check for both the old freebsd-historic and the proper | * FIFOs. We check for both the old freebsd-historic and the proper | ||||
* bindings-defined compatible strings for bcm2835, and also check the | * bindings-defined compatible strings for bcm2835, and also check the | ||||
* workaround the linux drivers use for rpi3, which is to override the | * workaround the linux drivers use for rpi3, which is to override the | ||||
* primecell periphid register value with a property. | * primecell periphid register value with a property. | ||||
*/ | */ | ||||
if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || | if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || | ||||
ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { | ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { | ||||
hwrev = 2; | return (2); | ||||
} else { | } else { | ||||
node = ofw_bus_get_node(sc->sc_dev); | node = ofw_bus_get_node(sc->sc_dev); | ||||
if (OF_getencprop(node, "arm,primecell-periphid", &periphid, | if (OF_getencprop(node, "arm,primecell-periphid", &periphid, | ||||
sizeof(periphid)) > 0) { | sizeof(periphid)) > 0) { | ||||
hwrev = (periphid >> 20) & 0x0f; | return ((periphid >> 20) & 0x0f); | ||||
} else { | |||||
hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; | |||||
} | } | ||||
} | } | ||||
#else | |||||
hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; | return (-1); | ||||
} | |||||
#endif | #endif | ||||
static int | |||||
uart_pl011_bus_probe(struct uart_softc *sc) | |||||
{ | |||||
int hwrev; | |||||
hwrev = -1; | |||||
#ifdef FDT | |||||
if (IS_FDT) | |||||
hwrev = uart_pl011_bus_hwrev_fdt(sc); | |||||
#endif | |||||
if (hwrev < 0) | |||||
hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; | |||||
if (hwrev <= 2) { | if (hwrev <= 2) { | ||||
sc->sc_rxfifosz = FIFO_RX_SIZE_R2; | sc->sc_rxfifosz = FIFO_RX_SIZE_R2; | ||||
sc->sc_txfifosz = FIFO_TX_SIZE_R2; | sc->sc_txfifosz = FIFO_TX_SIZE_R2; | ||||
} else { | } else { | ||||
sc->sc_rxfifosz = FIFO_RX_SIZE_R3; | sc->sc_rxfifosz = FIFO_RX_SIZE_R3; | ||||
sc->sc_txfifosz = FIFO_TX_SIZE_R3; | sc->sc_txfifosz = FIFO_TX_SIZE_R3; | ||||
} | } | ||||
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