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sys/dev/drm2/i915/i915_reg.h

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#define VGA0_PD_P1_MASK (0x1f << 0) #define VGA0_PD_P1_MASK (0x1f << 0)
#define VGA1_PD_P2_DIV_4 (1 << 15) #define VGA1_PD_P2_DIV_4 (1 << 15)
#define VGA1_PD_P1_DIV_2 (1 << 13) #define VGA1_PD_P1_DIV_2 (1 << 13)
#define VGA1_PD_P1_SHIFT 8 #define VGA1_PD_P1_SHIFT 8
#define VGA1_PD_P1_MASK (0x1f << 8) #define VGA1_PD_P1_MASK (0x1f << 8)
#define _DPLL_A 0x06014 #define _DPLL_A 0x06014
#define _DPLL_B 0x06018 #define _DPLL_B 0x06018
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
#define DPLL_VCO_ENABLE (1 << 31) #define DPLL_VCO_ENABLE (1U << 31)
#define DPLL_DVO_HIGH_SPEED (1 << 30) #define DPLL_DVO_HIGH_SPEED (1 << 30)
#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
#define DPLL_SYNCLOCK_ENABLE (1 << 29) #define DPLL_SYNCLOCK_ENABLE (1 << 29)
#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
#define DPLL_VGA_MODE_DIS (1 << 28) #define DPLL_VGA_MODE_DIS (1 << 28)
#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
#define DPLL_MODE_MASK (3 << 26) #define DPLL_MODE_MASK (3 << 26)
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#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
/* SDVO port control */ /* SDVO port control */
#define SDVOB 0x61140 #define SDVOB 0x61140
#define SDVOC 0x61160 #define SDVOC 0x61160
#define SDVO_ENABLE (1 << 31) #define SDVO_ENABLE (1U << 31)
#define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_PIPE_B_SELECT (1 << 30)
#define SDVO_STALL_SELECT (1 << 29) #define SDVO_STALL_SELECT (1 << 29)
#define SDVO_INTERRUPT_ENABLE (1 << 26) #define SDVO_INTERRUPT_ENABLE (1 << 26)
/** /**
* 915G/GM SDVO pixel multiplier. * 915G/GM SDVO pixel multiplier.
* *
* Programmed value is multiplier - 1, up to 5x. * Programmed value is multiplier - 1, up to 5x.
* *
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/* Bits to be preserved when writing */ /* Bits to be preserved when writing */
#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
/* DVO port control */ /* DVO port control */
#define DVOA 0x61120 #define DVOA 0x61120
#define DVOB 0x61140 #define DVOB 0x61140
#define DVOC 0x61160 #define DVOC 0x61160
#define DVO_ENABLE (1 << 31) #define DVO_ENABLE (1U << 31)
#define DVO_PIPE_B_SELECT (1 << 30) #define DVO_PIPE_B_SELECT (1 << 30)
#define DVO_PIPE_STALL_UNUSED (0 << 28) #define DVO_PIPE_STALL_UNUSED (0 << 28)
#define DVO_PIPE_STALL (1 << 28) #define DVO_PIPE_STALL (1 << 28)
#define DVO_PIPE_STALL_TV (2 << 28) #define DVO_PIPE_STALL_TV (2 << 28)
#define DVO_PIPE_STALL_MASK (3 << 28) #define DVO_PIPE_STALL_MASK (3 << 28)
#define DVO_USE_VGA_SYNC (1 << 15) #define DVO_USE_VGA_SYNC (1 << 15)
#define DVO_DATA_ORDER_I740 (0 << 14) #define DVO_DATA_ORDER_I740 (0 << 14)
#define DVO_DATA_ORDER_FP (1 << 14) #define DVO_DATA_ORDER_FP (1 << 14)
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#define DVO_SRCDIM_VERTICAL_SHIFT 0 #define DVO_SRCDIM_VERTICAL_SHIFT 0
/* LVDS port control */ /* LVDS port control */
#define LVDS 0x61180 #define LVDS 0x61180
/* /*
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
* the DPLL semantics change when the LVDS is assigned to that pipe. * the DPLL semantics change when the LVDS is assigned to that pipe.
*/ */
#define LVDS_PORT_EN (1 << 31) #define LVDS_PORT_EN (1U << 31)
/* Selects pipe B for LVDS data. Must be set on pre-965. */ /* Selects pipe B for LVDS data. Must be set on pre-965. */
#define LVDS_PIPEB_SELECT (1 << 30) #define LVDS_PIPEB_SELECT (1 << 30)
#define LVDS_PIPE_MASK (1 << 30) #define LVDS_PIPE_MASK (1 << 30)
#define LVDS_PIPE(pipe) ((pipe) << 30) #define LVDS_PIPE(pipe) ((pipe) << 30)
/* LVDS dithering flag on 965/g4x platform */ /* LVDS dithering flag on 965/g4x platform */
#define LVDS_ENABLE_DITHER (1 << 25) #define LVDS_ENABLE_DITHER (1 << 25)
/* LVDS sync polarity flags. Set to invert (i.e. negative) */ /* LVDS sync polarity flags. Set to invert (i.e. negative) */
#define LVDS_VSYNC_POLARITY (1 << 21) #define LVDS_VSYNC_POLARITY (1 << 21)
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/* Video Data Island Packet control */ /* Video Data Island Packet control */
#define VIDEO_DIP_DATA 0x61178 #define VIDEO_DIP_DATA 0x61178
/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
* of the infoframe structure specified by CEA-861. */ * of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32 #define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_CTL 0x61170 #define VIDEO_DIP_CTL 0x61170
/* Pre HSW: */ /* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31) #define VIDEO_DIP_ENABLE (1U << 31)
#define VIDEO_DIP_PORT_B (1 << 29) #define VIDEO_DIP_PORT_B (1 << 29)
#define VIDEO_DIP_PORT_C (2 << 29) #define VIDEO_DIP_PORT_C (2 << 29)
#define VIDEO_DIP_PORT_D (3 << 29) #define VIDEO_DIP_PORT_D (3 << 29)
#define VIDEO_DIP_PORT_MASK (3 << 29) #define VIDEO_DIP_PORT_MASK (3 << 29)
#define VIDEO_DIP_ENABLE_GCP (1 << 25) #define VIDEO_DIP_ENABLE_GCP (1 << 25)
#define VIDEO_DIP_ENABLE_AVI (1 << 21) #define VIDEO_DIP_ENABLE_AVI (1 << 21)
#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
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#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
/* Panel power sequencing */ /* Panel power sequencing */
#define PP_STATUS 0x61200 #define PP_STATUS 0x61200
#define PP_ON (1 << 31) #define PP_ON (1U << 31)
/* /*
* Indicates that all dependencies of the panel are on: * Indicates that all dependencies of the panel are on:
* *
* - PLL enabled * - PLL enabled
* - pipe enabled * - pipe enabled
* - LVDS/DVOB/DVOC on * - LVDS/DVOB/DVOC on
*/ */
#define PP_READY (1 << 30) #define PP_READY (1 << 30)
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#define PP_CONTROL 0x61204 #define PP_CONTROL 0x61204
#define POWER_TARGET_ON (1 << 0) #define POWER_TARGET_ON (1 << 0)
#define PP_ON_DELAYS 0x61208 #define PP_ON_DELAYS 0x61208
#define PP_OFF_DELAYS 0x6120c #define PP_OFF_DELAYS 0x6120c
#define PP_DIVISOR 0x61210 #define PP_DIVISOR 0x61210
/* Panel fitting */ /* Panel fitting */
#define PFIT_CONTROL 0x61230 #define PFIT_CONTROL 0x61230
#define PFIT_ENABLE (1 << 31) #define PFIT_ENABLE (1U << 31)
#define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29 #define PFIT_PIPE_SHIFT 29
#define VERT_INTERP_DISABLE (0 << 10) #define VERT_INTERP_DISABLE (0 << 10)
#define VERT_INTERP_BILINEAR (1 << 10) #define VERT_INTERP_BILINEAR (1 << 10)
#define VERT_INTERP_MASK (3 << 10) #define VERT_INTERP_MASK (3 << 10)
#define VERT_AUTO_SCALE (1 << 9) #define VERT_AUTO_SCALE (1 << 9)
#define HORIZ_INTERP_DISABLE (0 << 6) #define HORIZ_INTERP_DISABLE (0 << 6)
#define HORIZ_INTERP_BILINEAR (1 << 6) #define HORIZ_INTERP_BILINEAR (1 << 6)
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#define PFIT_VERT_SCALE_MASK_965 0x1fff0000 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
#define PFIT_HORIZ_SCALE_SHIFT_965 0 #define PFIT_HORIZ_SCALE_SHIFT_965 0
#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
#define PFIT_AUTO_RATIOS 0x61238 #define PFIT_AUTO_RATIOS 0x61238
/* Backlight control */ /* Backlight control */
#define BLC_PWM_CTL2 0x61250 /* 965+ only */ #define BLC_PWM_CTL2 0x61250 /* 965+ only */
#define BLM_PWM_ENABLE (1 << 31) #define BLM_PWM_ENABLE (1U << 31)
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
#define BLM_PIPE_SELECT (1 << 29) #define BLM_PIPE_SELECT (1 << 29)
#define BLM_PIPE_SELECT_IVB (3 << 29) #define BLM_PIPE_SELECT_IVB (3 << 29)
#define BLM_PIPE_A (0 << 29) #define BLM_PIPE_A (0 << 29)
#define BLM_PIPE_B (1 << 29) #define BLM_PIPE_B (1 << 29)
#define BLM_PIPE_C (2 << 29) /* ivb + */ #define BLM_PIPE_C (2 << 29) /* ivb + */
#define BLM_PIPE(pipe) ((pipe) << 29) #define BLM_PIPE(pipe) ((pipe) << 29)
#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
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/* New registers for PCH-split platforms. Safe where new bits show up, the /* New registers for PCH-split platforms. Safe where new bits show up, the
* register layout machtes with gen4 BLC_PWM_CTL[12]. */ * register layout machtes with gen4 BLC_PWM_CTL[12]. */
#define BLC_PWM_CPU_CTL2 0x48250 #define BLC_PWM_CPU_CTL2 0x48250
#define BLC_PWM_CPU_CTL 0x48254 #define BLC_PWM_CPU_CTL 0x48254
/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
* like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
#define BLC_PWM_PCH_CTL1 0xc8250 #define BLC_PWM_PCH_CTL1 0xc8250
#define BLM_PCH_PWM_ENABLE (1 << 31) #define BLM_PCH_PWM_ENABLE (1U << 31)
#define BLM_PCH_OVERRIDE_ENABLE (1 << 30) #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
#define BLM_PCH_POLARITY (1 << 29) #define BLM_PCH_POLARITY (1 << 29)
#define BLC_PWM_PCH_CTL2 0xc8254 #define BLC_PWM_PCH_CTL2 0xc8254
/* TV port control */ /* TV port control */
#define TV_CTL 0x68000 #define TV_CTL 0x68000
/** Enables the TV encoder */ /** Enables the TV encoder */
# define TV_ENC_ENABLE (1 << 31) # define TV_ENC_ENABLE (1U << 31)
/** Sources the TV encoder input from pipe B instead of A. */ /** Sources the TV encoder input from pipe B instead of A. */
# define TV_ENC_PIPEB_SELECT (1 << 30) # define TV_ENC_PIPEB_SELECT (1 << 30)
/** Outputs composite video (DAC A only) */ /** Outputs composite video (DAC A only) */
# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
/** Outputs SVideo video (DAC B/C) */ /** Outputs SVideo video (DAC B/C) */
# define TV_ENC_OUTPUT_SVIDEO (1 << 28) # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
/** Outputs Component video (DAC A/B/C) */ /** Outputs Component video (DAC A/B/C) */
# define TV_ENC_OUTPUT_COMPONENT (2 << 28) # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
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#define TV_DAC 0x68004 #define TV_DAC 0x68004
# define TV_DAC_SAVE 0x00ffff00 # define TV_DAC_SAVE 0x00ffff00
/** /**
* Reports that DAC state change logic has reported change (RO). * Reports that DAC state change logic has reported change (RO).
* *
* This gets cleared when TV_DAC_STATE_EN is cleared * This gets cleared when TV_DAC_STATE_EN is cleared
*/ */
# define TVDAC_STATE_CHG (1 << 31) # define TVDAC_STATE_CHG (1U << 31)
# define TVDAC_SENSE_MASK (7 << 28) # define TVDAC_SENSE_MASK (7 << 28)
/** Reports that DAC A voltage is above the detect threshold */ /** Reports that DAC A voltage is above the detect threshold */
# define TVDAC_A_SENSE (1 << 30) # define TVDAC_A_SENSE (1 << 30)
/** Reports that DAC B voltage is above the detect threshold */ /** Reports that DAC B voltage is above the detect threshold */
# define TVDAC_B_SENSE (1 << 29) # define TVDAC_B_SENSE (1 << 29)
/** Reports that DAC C voltage is above the detect threshold */ /** Reports that DAC C voltage is above the detect threshold */
# define TVDAC_C_SENSE (1 << 28) # define TVDAC_C_SENSE (1 << 28)
/** /**
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# define TV_HSYNC_END_MASK 0x1fff0000 # define TV_HSYNC_END_MASK 0x1fff0000
# define TV_HSYNC_END_SHIFT 16 # define TV_HSYNC_END_SHIFT 16
/** Total number of pixels minus one in the line (display and blanking). */ /** Total number of pixels minus one in the line (display and blanking). */
# define TV_HTOTAL_MASK 0x00001fff # define TV_HTOTAL_MASK 0x00001fff
# define TV_HTOTAL_SHIFT 0 # define TV_HTOTAL_SHIFT 0
#define TV_H_CTL_2 0x68034 #define TV_H_CTL_2 0x68034
/** Enables the colorburst (needed for non-component color) */ /** Enables the colorburst (needed for non-component color) */
# define TV_BURST_ENA (1 << 31) # define TV_BURST_ENA (1U << 31)
/** Offset of the colorburst from the start of hsync, in pixels minus one. */ /** Offset of the colorburst from the start of hsync, in pixels minus one. */
# define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_SHIFT 16
# define TV_HBURST_START_MASK 0x1fff0000 # define TV_HBURST_START_MASK 0x1fff0000
/** Length of the colorburst */ /** Length of the colorburst */
# define TV_HBURST_LEN_SHIFT 0 # define TV_HBURST_LEN_SHIFT 0
# define TV_HBURST_LEN_MASK 0x0001fff # define TV_HBURST_LEN_MASK 0x0001fff
#define TV_H_CTL_3 0x68038 #define TV_H_CTL_3 0x68038
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* Offset of the start of vsync in field 2, measured in one less than the * Offset of the start of vsync in field 2, measured in one less than the
* number of half lines. * number of half lines.
*/ */
# define TV_VSYNC_START_F2_MASK 0x0000007f # define TV_VSYNC_START_F2_MASK 0x0000007f
# define TV_VSYNC_START_F2_SHIFT 0 # define TV_VSYNC_START_F2_SHIFT 0
#define TV_V_CTL_3 0x68044 #define TV_V_CTL_3 0x68044
/** Enables generation of the equalization signal */ /** Enables generation of the equalization signal */
# define TV_EQUAL_ENA (1 << 31) # define TV_EQUAL_ENA (1U << 31)
/** Length of vsync, in half lines */ /** Length of vsync, in half lines */
# define TV_VEQ_LEN_MASK 0x007f0000 # define TV_VEQ_LEN_MASK 0x007f0000
# define TV_VEQ_LEN_SHIFT 16 # define TV_VEQ_LEN_SHIFT 16
/** Offset of the start of equalization in field 1, measured in one less than /** Offset of the start of equalization in field 1, measured in one less than
* the number of half lines. * the number of half lines.
*/ */
# define TV_VEQ_START_F1_MASK 0x0007f00 # define TV_VEQ_START_F1_MASK 0x0007f00
# define TV_VEQ_START_F1_SHIFT 8 # define TV_VEQ_START_F1_SHIFT 8
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* Offset to the end of vertical colorburst, measured in one less than the * Offset to the end of vertical colorburst, measured in one less than the
* number of lines from the start of NBR. * number of lines from the start of NBR.
*/ */
# define TV_VBURST_END_F4_MASK 0x000000ff # define TV_VBURST_END_F4_MASK 0x000000ff
# define TV_VBURST_END_F4_SHIFT 0 # define TV_VBURST_END_F4_SHIFT 0
#define TV_SC_CTL_1 0x68060 #define TV_SC_CTL_1 0x68060
/** Turns on the first subcarrier phase generation DDA */ /** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA1_EN (1 << 31) # define TV_SC_DDA1_EN (1U << 31)
/** Turns on the first subcarrier phase generation DDA */ /** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA2_EN (1 << 30) # define TV_SC_DDA2_EN (1 << 30)
/** Turns on the first subcarrier phase generation DDA */ /** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA3_EN (1 << 29) # define TV_SC_DDA3_EN (1 << 29)
/** Sets the subcarrier DDA to reset frequency every other field */ /** Sets the subcarrier DDA to reset frequency every other field */
# define TV_SC_RESET_EVERY_2 (0 << 24) # define TV_SC_RESET_EVERY_2 (0 << 24)
/** Sets the subcarrier DDA to reset frequency every fourth field */ /** Sets the subcarrier DDA to reset frequency every fourth field */
# define TV_SC_RESET_EVERY_4 (1 << 24) # define TV_SC_RESET_EVERY_4 (1 << 24)
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#define TV_FILTER_CTL_1 0x68080 #define TV_FILTER_CTL_1 0x68080
/** /**
* Enables automatic scaling calculation. * Enables automatic scaling calculation.
* *
* If set, the rest of the registers are ignored, and the calculated values can * If set, the rest of the registers are ignored, and the calculated values can
* be read back from the register. * be read back from the register.
*/ */
# define TV_AUTO_SCALE (1 << 31) # define TV_AUTO_SCALE (1U << 31)
/** /**
* Disables the vertical filter. * Disables the vertical filter.
* *
* This is required on modes more than 1024 pixels wide */ * This is required on modes more than 1024 pixels wide */
# define TV_V_FILTER_BYPASS (1 << 29) # define TV_V_FILTER_BYPASS (1 << 29)
/** Enables adaptive vertical filtering */ /** Enables adaptive vertical filtering */
# define TV_VADAPT (1 << 28) # define TV_VADAPT (1 << 28)
# define TV_VADAPT_MODE_MASK (3 << 26) # define TV_VADAPT_MODE_MASK (3 << 26)
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* For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
* *
* \sa TV_VSCALE_IP_INT_MASK * \sa TV_VSCALE_IP_INT_MASK
*/ */
# define TV_VSCALE_IP_FRAC_MASK 0x00007fff # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
# define TV_VSCALE_IP_FRAC_SHIFT 0 # define TV_VSCALE_IP_FRAC_SHIFT 0
#define TV_CC_CONTROL 0x68090 #define TV_CC_CONTROL 0x68090
# define TV_CC_ENABLE (1 << 31) # define TV_CC_ENABLE (1U << 31)
/** /**
* Specifies which field to send the CC data in. * Specifies which field to send the CC data in.
* *
* CC data is usually sent in field 0. * CC data is usually sent in field 0.
*/ */
# define TV_CC_FID_MASK (1 << 27) # define TV_CC_FID_MASK (1 << 27)
# define TV_CC_FID_SHIFT 27 # define TV_CC_FID_SHIFT 27
/** Sets the horizontal position of the CC data. Usually 135. */ /** Sets the horizontal position of the CC data. Usually 135. */
# define TV_CC_HOFF_MASK 0x03ff0000 # define TV_CC_HOFF_MASK 0x03ff0000
# define TV_CC_HOFF_SHIFT 16 # define TV_CC_HOFF_SHIFT 16
/** Sets the vertical position of the CC data. Usually 21 */ /** Sets the vertical position of the CC data. Usually 21 */
# define TV_CC_LINE_MASK 0x0000003f # define TV_CC_LINE_MASK 0x0000003f
# define TV_CC_LINE_SHIFT 0 # define TV_CC_LINE_SHIFT 0
#define TV_CC_DATA 0x68094 #define TV_CC_DATA 0x68094
# define TV_CC_RDY (1 << 31) # define TV_CC_RDY (1U << 31)
/** Second word of CC data to be transmitted. */ /** Second word of CC data to be transmitted. */
# define TV_CC_DATA_2_MASK 0x007f0000 # define TV_CC_DATA_2_MASK 0x007f0000
# define TV_CC_DATA_2_SHIFT 16 # define TV_CC_DATA_2_SHIFT 16
/** First word of CC data to be transmitted. */ /** First word of CC data to be transmitted. */
# define TV_CC_DATA_1_MASK 0x0000007f # define TV_CC_DATA_1_MASK 0x0000007f
# define TV_CC_DATA_1_SHIFT 0 # define TV_CC_DATA_1_SHIFT 0
#define TV_H_LUMA_0 0x68100 #define TV_H_LUMA_0 0x68100
#define TV_H_LUMA_59 0x681ec #define TV_H_LUMA_59 0x681ec
#define TV_H_CHROMA_0 0x68200 #define TV_H_CHROMA_0 0x68200
#define TV_H_CHROMA_59 0x682ec #define TV_H_CHROMA_59 0x682ec
#define TV_V_LUMA_0 0x68300 #define TV_V_LUMA_0 0x68300
#define TV_V_LUMA_42 0x683a8 #define TV_V_LUMA_42 0x683a8
#define TV_V_CHROMA_0 0x68400 #define TV_V_CHROMA_0 0x68400
#define TV_V_CHROMA_42 0x684a8 #define TV_V_CHROMA_42 0x684a8
/* Display Port */ /* Display Port */
#define DP_A 0x64000 /* eDP */ #define DP_A 0x64000 /* eDP */
#define DP_B 0x64100 #define DP_B 0x64100
#define DP_C 0x64200 #define DP_C 0x64200
#define DP_D 0x64300 #define DP_D 0x64300
#define DP_PORT_EN (1 << 31) #define DP_PORT_EN (1U << 31)
#define DP_PIPEB_SELECT (1 << 30) #define DP_PIPEB_SELECT (1 << 30)
#define DP_PIPE_MASK (1 << 30) #define DP_PIPE_MASK (1 << 30)
/* Link training mode - select a suitable mode for each stage */ /* Link training mode - select a suitable mode for each stage */
#define DP_LINK_TRAIN_PAT_1 (0 << 28) #define DP_LINK_TRAIN_PAT_1 (0 << 28)
#define DP_LINK_TRAIN_PAT_2 (1 << 28) #define DP_LINK_TRAIN_PAT_2 (1 << 28)
#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
#define DP_LINK_TRAIN_OFF (3 << 28) #define DP_LINK_TRAIN_OFF (3 << 28)
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#define DPD_AUX_CH_CTL 0x64310 #define DPD_AUX_CH_CTL 0x64310
#define DPD_AUX_CH_DATA1 0x64314 #define DPD_AUX_CH_DATA1 0x64314
#define DPD_AUX_CH_DATA2 0x64318 #define DPD_AUX_CH_DATA2 0x64318
#define DPD_AUX_CH_DATA3 0x6431c #define DPD_AUX_CH_DATA3 0x6431c
#define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA4 0x64320
#define DPD_AUX_CH_DATA5 0x64324 #define DPD_AUX_CH_DATA5 0x64324
#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) #define DP_AUX_CH_CTL_SEND_BUSY (1U << 31)
#define DP_AUX_CH_CTL_DONE (1 << 30) #define DP_AUX_CH_CTL_DONE (1 << 30)
#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
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#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
/* VBIOS regs */ /* VBIOS regs */
#define VGACNTRL 0x71400 #define VGACNTRL 0x71400
# define VGA_DISP_DISABLE (1 << 31) # define VGA_DISP_DISABLE (1U << 31)
# define VGA_2X_MODE (1 << 30) # define VGA_2X_MODE (1 << 30)
# define VGA_PIPE_B_SELECT (1 << 29) # define VGA_PIPE_B_SELECT (1 << 29)
/* Ironlake */ /* Ironlake */
#define CPU_VGACNTRL 0x41000 #define CPU_VGACNTRL 0x41000
#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
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#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
/* legacy palette */ /* legacy palette */
#define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800 #define _LGC_PALETTE_B 0x4a800
#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
/* interrupts */ /* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31) #define DE_MASTER_IRQ_CONTROL (1U << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29) #define DE_SPRITEB_FLIP_DONE (1 << 29)
#define DE_SPRITEA_FLIP_DONE (1 << 28) #define DE_SPRITEA_FLIP_DONE (1 << 28)
#define DE_PLANEB_FLIP_DONE (1 << 27) #define DE_PLANEB_FLIP_DONE (1 << 27)
#define DE_PLANEA_FLIP_DONE (1 << 26) #define DE_PLANEA_FLIP_DONE (1 << 26)
#define DE_PCU_EVENT (1 << 25) #define DE_PCU_EVENT (1 << 25)
#define DE_GTT_FAULT (1 << 24) #define DE_GTT_FAULT (1 << 24)
#define DE_POISON (1 << 23) #define DE_POISON (1 << 23)
#define DE_PERFORM_COUNTER (1 << 22) #define DE_PERFORM_COUNTER (1 << 22)
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#define SDE_TRANSB_CRC_ERR (1 << 4) #define SDE_TRANSB_CRC_ERR (1 << 4)
#define SDE_TRANSB_FIFO_UNDER (1 << 3) #define SDE_TRANSB_FIFO_UNDER (1 << 3)
#define SDE_TRANSA_CRC_DONE (1 << 2) #define SDE_TRANSA_CRC_DONE (1 << 2)
#define SDE_TRANSA_CRC_ERR (1 << 1) #define SDE_TRANSA_CRC_ERR (1 << 1)
#define SDE_TRANSA_FIFO_UNDER (1 << 0) #define SDE_TRANSA_FIFO_UNDER (1 << 0)
#define SDE_TRANS_MASK (0x3f) #define SDE_TRANS_MASK (0x3f)
/* south display engine interrupt: CPT/PPT */ /* south display engine interrupt: CPT/PPT */
#define SDE_AUDIO_POWER_D_CPT (1 << 31) #define SDE_AUDIO_POWER_D_CPT (1U << 31)
#define SDE_AUDIO_POWER_C_CPT (1 << 30) #define SDE_AUDIO_POWER_C_CPT (1 << 30)
#define SDE_AUDIO_POWER_B_CPT (1 << 29) #define SDE_AUDIO_POWER_B_CPT (1 << 29)
#define SDE_AUDIO_POWER_SHIFT_CPT 29 #define SDE_AUDIO_POWER_SHIFT_CPT 29
#define SDE_AUDIO_POWER_MASK_CPT (7 << 29) #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
#define SDE_AUXD_CPT (1 << 27) #define SDE_AUXD_CPT (1 << 27)
#define SDE_AUXC_CPT (1 << 26) #define SDE_AUXC_CPT (1 << 26)
#define SDE_AUXB_CPT (1 << 25) #define SDE_AUXB_CPT (1 << 25)
#define SDE_AUX_MASK_CPT (7 << 25) #define SDE_AUX_MASK_CPT (7 << 25)
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#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
#define FDI_PLL_CTL_1 0xfe000 #define FDI_PLL_CTL_1 0xfe000
#define FDI_PLL_CTL_2 0xfe004 #define FDI_PLL_CTL_2 0xfe004
/* or SDVOB */ /* or SDVOB */
#define HDMIB 0xe1140 #define HDMIB 0xe1140
#define PORT_ENABLE (1 << 31) #define PORT_ENABLE (1U << 31)
#define TRANSCODER(pipe) ((pipe) << 30) #define TRANSCODER(pipe) ((pipe) << 30)
#define TRANSCODER_CPT(pipe) ((pipe) << 29) #define TRANSCODER_CPT(pipe) ((pipe) << 29)
#define TRANSCODER_MASK (1 << 30) #define TRANSCODER_MASK (1 << 30)
#define TRANSCODER_MASK_CPT (3 << 29) #define TRANSCODER_MASK_CPT (3 << 29)
#define COLOR_FORMAT_8bpc (0) #define COLOR_FORMAT_8bpc (0)
#define COLOR_FORMAT_12bpc (3 << 26) #define COLOR_FORMAT_12bpc (3 << 26)
#define SDVOB_HOTPLUG_ENABLE (1 << 23) #define SDVOB_HOTPLUG_ENABLE (1 << 23)
#define SDVO_ENCODING (0) #define SDVO_ENCODING (0)
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