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sys/x86/include/specialreg.h
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#define CPUPT_PRW (1 << 4) /* PTWRITE Supported */ | #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */ | ||||
#define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */ | #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */ | ||||
/* Leaf 0 ecx. */ | /* Leaf 0 ecx. */ | ||||
#define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */ | #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */ | ||||
#define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */ | #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */ | ||||
#define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */ | #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */ | ||||
#define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */ | #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */ | ||||
#define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */ | #define CPUPT_LINEAR_IP (1U << 31) /* IP Payloads are Linear IP, otherwise IP is effective */ | ||||
kib: This one is fine. | |||||
/* Leaf 1 eax. */ | /* Leaf 1 eax. */ | ||||
#define CPUPT_NADDR_S 0 /* Number of Address Ranges */ | #define CPUPT_NADDR_S 0 /* Number of Address Ranges */ | ||||
#define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S) | #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S) | ||||
#define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */ | #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */ | ||||
#define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S) | #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S) | ||||
/* Leaf 1 ebx. */ | /* Leaf 1 ebx. */ | ||||
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This one is fine.