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Show First 20 Lines • Show All 183 Lines • ▼ Show 20 Lines	#define JZ_CLKGR0 0x00000020 /* Clock Gating Registers */
#define CLK_MAC (1 << 23)		#define CLK_MAC (1 << 23)
#define CLK_UHC (1 << 24)		#define CLK_UHC (1 << 24)
#define CLK_SMB2 (1 << 25)		#define CLK_SMB2 (1 << 25)
#define CLK_CIM (1 << 26)		#define CLK_CIM (1 << 26)
#define CLK_TVE (1 << 27)		#define CLK_TVE (1 << 27)
#define CLK_LCD (1 << 28)		#define CLK_LCD (1 << 28)
#define CLK_IPU (1 << 29)		#define CLK_IPU (1 << 29)
#define CLK_DDR0 (1 << 30)		#define CLK_DDR0 (1 << 30)
#define CLK_DDR1 (1 << 31)		#define CLK_DDR1 (1U << 31)
#define JZ_CLKGR1 0x00000028 /* Clock Gating Registers */		#define JZ_CLKGR1 0x00000028 /* Clock Gating Registers */
#define CLK_SMB3 (1 << 0)		#define CLK_SMB3 (1 << 0)
#define CLK_TSSI1 (1 << 1)		#define CLK_TSSI1 (1 << 1)
#define CLK_VPU (1 << 2)		#define CLK_VPU (1 << 2)
#define CLK_PCM (1 << 3)		#define CLK_PCM (1 << 3)
#define CLK_GPU (1 << 4)		#define CLK_GPU (1 << 4)
#define CLK_COMPRESS (1 << 5)		#define CLK_COMPRESS (1 << 5)
#define CLK_AIC1 (1 << 6)		#define CLK_AIC1 (1 << 6)
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