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	#define BP_NUM_IRQS 32			#define BP_NUM_IRQS 32
	/* We use hard irqs 15-31 as soft */			/* We use hard irqs 15-31 as soft */
	#define BP_FIRST_SOFT 16			#define BP_FIRST_SOFT 16

	#define BP_CFG_IRQ_S 0			#define BP_CFG_IRQ_S 0
	#define BP_CFG_IRQ_M (0xf << BP_CFG_IRQ_S)			#define BP_CFG_IRQ_M (0xf << BP_CFG_IRQ_S)
	#define BP_CFG_TID_S 8			#define BP_CFG_TID_S 8
	#define BP_CFG_TID_M (0x7FFFFF << BP_CFG_TID_S)			#define BP_CFG_TID_M (0x7FFFFF << BP_CFG_TID_S)
	#define BP_CFG_ENABLE (1 << 31)			#define BP_CFG_ENABLE (1U << 31)

	enum {			enum {
	BP_CFG,			BP_CFG,
	BP_IP_READ,			BP_IP_READ,
	BP_IP_SET,			BP_IP_SET,
	BP_IP_CLEAR			BP_IP_CLEAR
	};			};

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