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sys/dev/usb/controller/saf1761_otg_reg.h
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#define SOTG_INTERRUPT_CFG_DEBUG_SET (1 << 16) | #define SOTG_INTERRUPT_CFG_DEBUG_SET (1 << 16) | ||||
#define SOTG_INTERRUPT_CFG_CDBGMOD (1 << 6) /* ACK only */ | #define SOTG_INTERRUPT_CFG_CDBGMOD (1 << 6) /* ACK only */ | ||||
#define SOTG_INTERRUPT_CFG_DDBGMODIN (1 << 4) /* ACK only */ | #define SOTG_INTERRUPT_CFG_DDBGMODIN (1 << 4) /* ACK only */ | ||||
#define SOTG_INTERRUPT_CFG_DDBGMODOUT (1 << 2) /* ACK and NYET only */ | #define SOTG_INTERRUPT_CFG_DDBGMODOUT (1 << 2) /* ACK and NYET only */ | ||||
#define SOTG_INTERRUPT_CFG_INTLVL (1 << 1) | #define SOTG_INTERRUPT_CFG_INTLVL (1 << 1) | ||||
#define SOTG_INTERRUPT_CFG_INTPOL (1 << 0) | #define SOTG_INTERRUPT_CFG_INTPOL (1 << 0) | ||||
#define SOTG_DCINTERRUPT_EN 0x214 | #define SOTG_DCINTERRUPT_EN 0x214 | ||||
#define SOTG_HW_MODE_CTRL 0x300 | #define SOTG_HW_MODE_CTRL 0x300 | ||||
#define SOTG_HW_MODE_CTRL_ALL_ATX_RESET (1 << 31) | #define SOTG_HW_MODE_CTRL_ALL_ATX_RESET (1U << 31) | ||||
#define SOTG_HW_MODE_CTRL_ANA_DIGI_OC (1 << 15) | #define SOTG_HW_MODE_CTRL_ANA_DIGI_OC (1 << 15) | ||||
#define SOTG_HW_MODE_CTRL_DEV_DMA (1 << 11) | #define SOTG_HW_MODE_CTRL_DEV_DMA (1 << 11) | ||||
#define SOTG_HW_MODE_CTRL_COMN_INT (1 << 10) | #define SOTG_HW_MODE_CTRL_COMN_INT (1 << 10) | ||||
#define SOTG_HW_MODE_CTRL_COMN_DMA (1 << 9) | #define SOTG_HW_MODE_CTRL_COMN_DMA (1 << 9) | ||||
#define SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH (1 << 8) | #define SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH (1 << 8) | ||||
#define SOTG_HW_MODE_CTRL_DACK_POL (1 << 6) | #define SOTG_HW_MODE_CTRL_DACK_POL (1 << 6) | ||||
#define SOTG_HW_MODE_CTRL_DREQ_POL (1 << 5) | #define SOTG_HW_MODE_CTRL_DREQ_POL (1 << 5) | ||||
#define SOTG_HW_MODE_CTRL_INTR_POL (1 << 2) | #define SOTG_HW_MODE_CTRL_INTR_POL (1 << 2) | ||||
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