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Differential D13858 Diff 37788 sys/dev/uart/uart_dev_mvebu.c

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sys/dev/uart/uart_dev_mvebu.c

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#define RBR_BRK_DET (1 << 15) /* Break Detect */ #define RBR_BRK_DET (1 << 15) /* Break Detect */
#define RBR_FRM_ERR_DET (1 << 14) /* Frame Error Detect */ #define RBR_FRM_ERR_DET (1 << 14) /* Frame Error Detect */
#define RBR_PAR_ERR_DET (1 << 13) /* Parity Error Detect */ #define RBR_PAR_ERR_DET (1 << 13) /* Parity Error Detect */
#define RBR_OVR_ERR_DET (1 << 12) /* Overrun Error */ #define RBR_OVR_ERR_DET (1 << 12) /* Overrun Error */
#define UART_TSH 0x04 /* Transmitter Holding Register */ #define UART_TSH 0x04 /* Transmitter Holding Register */
#define UART_CTRL 0x08 /* Control Register */ #define UART_CTRL 0x08 /* Control Register */
#define CTRL_SOFT_RST (1 << 31) /* Soft Reset */ #define CTRL_SOFT_RST (1U << 31) /* Soft Reset */
#define CTRL_TX_FIFO_RST (1 << 15) /* TX FIFO Reset */ #define CTRL_TX_FIFO_RST (1 << 15) /* TX FIFO Reset */
#define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */ #define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */
#define CTRL_ST_MIRR_EN (1 << 13) /* Status Mirror Enable */ #define CTRL_ST_MIRR_EN (1 << 13) /* Status Mirror Enable */
#define CTRL_LPBK_EN (1 << 12) /* Loopback Mode Enable */ #define CTRL_LPBK_EN (1 << 12) /* Loopback Mode Enable */
#define CTRL_SND_BRK_SEQ (1 << 11) /* Send Break Sequence */ #define CTRL_SND_BRK_SEQ (1 << 11) /* Send Break Sequence */
#define CTRL_PAR_EN (1 << 10) /* Parity Enable */ #define CTRL_PAR_EN (1 << 10) /* Parity Enable */
#define CTRL_TWO_STOP (1 << 9) /* Two Stop Bits */ #define CTRL_TWO_STOP (1 << 9) /* Two Stop Bits */
#define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */ #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */
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