Differential D13858 Diff 37788 sys/dev/ixgbe/ixgbe_type.h

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sys/dev/ixgbe/ixgbe_type.h

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	#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)			#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
	#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)			#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
	#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)			#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
	#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)			#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
	#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)			#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
	#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)			#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
	#define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28)			#define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28)
	#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)			#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
	#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)			#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1U << 31)

	#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)			#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)
	#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)			#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)
	#define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1)			#define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1)
	#define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2)			#define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2)
	#define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2)			#define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2)
	#define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3)			#define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3)
	#define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29)			#define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29)
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	#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)			#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
	#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)			#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)

	#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)			#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)

	#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)			#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)
	#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)			#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)
	#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)			#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)
	#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31)			#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1U << 31)

	#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144			#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
	#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148			#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148

	#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0			#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0
	#define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF			#define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF
	#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18			#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18
	#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \			#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
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