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sys/dev/iwm/if_iwmreg.h
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#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) | #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) | ||||
#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ | #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ | ||||
#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ | #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ | ||||
#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ | #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ | ||||
/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), | ||||
* acknowledged (reset) by host writing "1" to flagged bits. */ | * acknowledged (reset) by host writing "1" to flagged bits. */ | ||||
#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ | #define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ | ||||
#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ | #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ | ||||
#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ | #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ | ||||
#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ | #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ | ||||
#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ | #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ | ||||
#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ | #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ | ||||
#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ | #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ | ||||
#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ | #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ | ||||
#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ | #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ | ||||
#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ | #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ | ||||
#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ | #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ | ||||
#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ | #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ | ||||
IWM_CSR_INT_BIT_HW_ERR | \ | IWM_CSR_INT_BIT_HW_ERR | \ | ||||
IWM_CSR_INT_BIT_FH_TX | \ | IWM_CSR_INT_BIT_FH_TX | \ | ||||
IWM_CSR_INT_BIT_SW_ERR | \ | IWM_CSR_INT_BIT_SW_ERR | \ | ||||
IWM_CSR_INT_BIT_RF_KILL | \ | IWM_CSR_INT_BIT_RF_KILL | \ | ||||
IWM_CSR_INT_BIT_SW_RX | \ | IWM_CSR_INT_BIT_SW_RX | \ | ||||
IWM_CSR_INT_BIT_WAKEUP | \ | IWM_CSR_INT_BIT_WAKEUP | \ | ||||
IWM_CSR_INT_BIT_ALIVE | \ | IWM_CSR_INT_BIT_ALIVE | \ | ||||
IWM_CSR_INT_BIT_RX_PERIODIC) | IWM_CSR_INT_BIT_RX_PERIODIC) | ||||
/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ | ||||
#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ | #define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ | ||||
#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ | #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ | ||||
#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ | #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ | ||||
#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ | #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ | ||||
#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ | #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ | ||||
#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ | #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ | ||||
#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ | #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ | ||||
IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ | IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ | ||||
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/* ANA_PLL */ | /* ANA_PLL */ | ||||
#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) | #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) | ||||
/* HPET MEM debug */ | /* HPET MEM debug */ | ||||
#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) | #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) | ||||
/* DRAM INT TABLE */ | /* DRAM INT TABLE */ | ||||
#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) | #define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31) | ||||
#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) | #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) | ||||
#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) | #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) | ||||
/* SECURE boot registers */ | /* SECURE boot registers */ | ||||
#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) | #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) | ||||
enum iwm_secure_boot_config_reg { | enum iwm_secure_boot_config_reg { | ||||
IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, | IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, | ||||
IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, | IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, | ||||
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* used with setting interrupt coalescing timer | * used with setting interrupt coalescing timer | ||||
* the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | ||||
* | * | ||||
* default interrupt coalescing timer is 64 x 32 = 2048 usecs | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | ||||
*/ | */ | ||||
#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) | #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) | ||||
#define IWM_HOST_INT_TIMEOUT_DEF (0x40) | #define IWM_HOST_INT_TIMEOUT_DEF (0x40) | ||||
#define IWM_HOST_INT_TIMEOUT_MIN (0x0) | #define IWM_HOST_INT_TIMEOUT_MIN (0x0) | ||||
#define IWM_HOST_INT_OPER_MODE (1 << 31) | #define IWM_HOST_INT_OPER_MODE (1U << 31) | ||||
/***************************************************************************** | /***************************************************************************** | ||||
* 7000/3000 series SHR DTS addresses * | * 7000/3000 series SHR DTS addresses * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
/* Diode Results Register Structure: */ | /* Diode Results Register Structure: */ | ||||
enum iwm_dtd_diode_reg { | enum iwm_dtd_diode_reg { | ||||
IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ | IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ | ||||
▲ Show 20 Lines • Show All 3,626 Lines • ▼ Show 20 Lines | enum iwm_tx_flags { | ||||
IWM_TX_CMD_FLG_AGG_START = (1 << 19), | IWM_TX_CMD_FLG_AGG_START = (1 << 19), | ||||
IWM_TX_CMD_FLG_MH_PAD = (1 << 20), | IWM_TX_CMD_FLG_MH_PAD = (1 << 20), | ||||
IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), | IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), | ||||
IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), | IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), | ||||
IWM_TX_CMD_FLG_DUR = (1 << 25), | IWM_TX_CMD_FLG_DUR = (1 << 25), | ||||
IWM_TX_CMD_FLG_FW_DROP = (1 << 26), | IWM_TX_CMD_FLG_FW_DROP = (1 << 26), | ||||
IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), | IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), | ||||
IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), | IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), | ||||
IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) | IWM_TX_CMD_FLG_HCCA_CHUNK = (1U << 31) | ||||
}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ | }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ | ||||
/** | /** | ||||
* enum iwm_tx_pm_timeouts - pm timeout values in TX command | * enum iwm_tx_pm_timeouts - pm timeout values in TX command | ||||
* @IWM_PM_FRAME_NONE: no need to suspend sleep mode | * @IWM_PM_FRAME_NONE: no need to suspend sleep mode | ||||
* @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU | * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU | ||||
* @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec | * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec | ||||
*/ | */ | ||||
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